From patchwork Fri May 23 19:01:49 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Badal Nilawar X-Patchwork-Id: 891929 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D779E29B208; Fri, 23 May 2025 19:00:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748026807; cv=none; b=IiyzBR9rmLPjSHXM/EDOkG/ef+SmXm/vYxHkwt4Kq6r1jVBm5yOjOzwlFNN86kfDLdceVba6NNdxBttA6u6B2RvXJrap+6VrutaPANP2fmaXQ8bYvOJipKvFScotpzJOZiKbRwSemB4+ihoVjhB4mxaEUebKJ7QNu065mf35izQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748026807; c=relaxed/simple; bh=lxHKZKVOenroNxh0FcZyRwd8gvSEvY446e/mnHo3N/0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=uejSOveJz2nV3RNWDcW+f3H0Ni2LYU7Ugt7ws/yRoAZWcKieqzW4uLs6UpqVaSHrP8PTz+Tx1yjsF6CAuso1GDhzLIL4c3JFS5t367xXEvqPbeM95btJAwvYB4epMSzJ0r39e4RBzLNRvMXQ+XJtvNXqaKxxx/FZvDgCPJ1SCz8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nvBI26qd; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nvBI26qd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1748026806; x=1779562806; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lxHKZKVOenroNxh0FcZyRwd8gvSEvY446e/mnHo3N/0=; b=nvBI26qd212iy5r7NFcLhSsZdZaAsaxGcZg9F+cDSTGfTY/bvphcqOQo lSPABDBepwji2z9w2lcYFij1BKeFEZXpegr8q1SUV8PnzlFMUYGaLZVWL 3hLt8yFDE20aDLC3IchT8uzRi/cHqAqXsq3DX5PvqZoT6rdVVPZS6qPBX f0keT18fbIz/xluad+R76FZG1uZsoMRByzHFOieyY0UxkTAXHDuMTM3fg //J0baR1rFDH4zWxFFCWBTteIewOqEwgVW1GoVZ2y05texNFDvQDpxMMx pEtADyQexqS90MQF7+2iyjcEUjJLYE3UF/3IKabxTY3taiHUn/1GP8yO4 g==; X-CSE-ConnectionGUID: i/HnxDAHQ32M81OV0y53Ww== X-CSE-MsgGUID: e+rp2XAASLGMCDPlIyD5MA== X-IronPort-AV: E=McAfee;i="6700,10204,11441"; a="61498516" X-IronPort-AV: E=Sophos;i="6.15,309,1739865600"; d="scan'208";a="61498516" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2025 12:00:06 -0700 X-CSE-ConnectionGUID: 5HK9La26SDSnlPEdLHQYYg== X-CSE-MsgGUID: WkCLMfuwQ5u1YVLMrwAFEA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,309,1739865600"; d="scan'208";a="141758939" Received: from unknown (HELO bnilawar-desk2.iind.intel.com) ([10.190.239.41]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 May 2025 12:00:02 -0700 From: Badal Nilawar To: intel-xe@lists.freedesktop.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org Cc: anshuman.gupta@intel.com, rafael@kernel.org, lenb@kernel.org, bhelgaas@google.com, ilpo.jarvinen@linux.intel.com, lucas.demarchi@intel.com, rodrigo.vivi@intel.com, varun.gupta@intel.com, ville.syrjala@linux.intel.com, uma.shankar@intel.com Subject: [PATCH v3 05/11] drm/xe/vrsr: Detect VRSR Capability Date: Sat, 24 May 2025 00:31:49 +0530 Message-Id: <20250523190155.2623462-6-badal.nilawar@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250523190155.2623462-1-badal.nilawar@intel.com> References: <20250523190155.2623462-1-badal.nilawar@intel.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Anshuman Gupta Detect VRAM Self Refresh(vrsr) Capability. Reviewed-by: Rodrigo Vivi Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/xe/regs/xe_regs.h | 3 +++ drivers/gpu/drm/xe/xe_device_types.h | 4 ++++ drivers/gpu/drm/xe/xe_pm.c | 26 ++++++++++++++++++++++++++ 3 files changed, 33 insertions(+) diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h index 3abb17d2ca33..4db486fb310a 100644 --- a/drivers/gpu/drm/xe/regs/xe_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_regs.h @@ -53,6 +53,9 @@ #define MTL_MPE_FREQUENCY XE_REG(0x13802c) #define MTL_RPE_MASK REG_GENMASK(8, 0) +#define VRAM_SR_CAPABILITY XE_REG(0x138144) +#define VRAM_SR_SUPPORTED REG_BIT(0) + #define VF_CAP_REG XE_REG(0x1901f8, XE_REG_OPTION_VF) #define VF_CAP REG_BIT(0) diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index e2749ed2a61f..3a15b3a252fd 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -512,6 +512,9 @@ struct xe_device { /** @d3cold.allowed: Indicates if d3cold is a valid device state */ bool allowed; + /** @d3cold.vrsr_capable: Indicates if d3cold VRAM Self Refresh is supported */ + bool vrsr_capable; + /** * @d3cold.vram_threshold: * @@ -522,6 +525,7 @@ struct xe_device { * Default threshold value is 300mb. */ u32 vram_threshold; + /** @d3cold.lock: protect vram_threshold */ struct mutex lock; } d3cold; diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c index 693866def183..c9395e62d21d 100644 --- a/drivers/gpu/drm/xe/xe_pm.c +++ b/drivers/gpu/drm/xe/xe_pm.c @@ -13,13 +13,16 @@ #include #include "display/xe_display.h" +#include "regs/xe_regs.h" #include "xe_bo.h" #include "xe_bo_evict.h" #include "xe_device.h" +#include "xe_force_wake.h" #include "xe_ggtt.h" #include "xe_gt.h" #include "xe_guc.h" #include "xe_irq.h" +#include "xe_mmio.h" #include "xe_pcode.h" #include "xe_pxp.h" #include "xe_trace.h" @@ -235,6 +238,28 @@ static bool xe_pm_pci_d3cold_capable(struct xe_device *xe) return true; } +static bool xe_pm_vrsr_capable(struct xe_device *xe) +{ + struct xe_mmio *mmio = xe_root_tile_mmio(xe); + unsigned int fw_ref; + struct xe_gt *gt; + u32 val; + + gt = xe_root_mmio_gt(xe); + + if (!xe->info.probe_display) + return false; + + fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); + if (!fw_ref) + return false; + + val = xe_mmio_read32(mmio, VRAM_SR_CAPABILITY); + xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL); + + return val & VRAM_SR_SUPPORTED; +} + static void xe_pm_runtime_init(struct xe_device *xe) { struct device *dev = xe->drm.dev; @@ -349,6 +374,7 @@ int xe_pm_init(struct xe_device *xe) err = xe_pm_set_vram_threshold(xe, vram_threshold); if (err) goto err_unregister; + xe->d3cold.vrsr_capable = xe_pm_vrsr_capable(xe); } xe_pm_runtime_init(xe);