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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SA2PEPF000015CC.mail.protection.outlook.com (10.167.241.202) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8230.7 via Frontend Transport; Sat, 30 Nov 2024 14:07:44 +0000 Received: from AUS-P9-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Sat, 30 Nov 2024 08:07:42 -0600 From: Mario Limonciello To: Borislav Petkov CC: Thomas Gleixner , Ingo Molnar , "Dave Hansen" , "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "H . Peter Anvin" , "Rafael J . Wysocki" , "Gautham R . Shenoy" , Mario Limonciello , Perry Yuan , Brijesh Singh , Peter Zijlstra , Li RongQing , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "open list:ACPI" , "open list:AMD PSTATE DRIVER" , Pawan Gupta Subject: [PATCH v7 03/12] x86/msr-index: define AMD heterogeneous CPU related MSR Date: Sat, 30 Nov 2024 08:06:54 -0600 Message-ID: <20241130140703.557-4-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241130140703.557-1-mario.limonciello@amd.com> References: <20241130140703.557-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CC:EE_|CYXPR12MB9339:EE_ X-MS-Office365-Filtering-Correlation-Id: 8ce1e6fd-8163-43a9-612c-08dd11485c9e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|82310400026|7416014|36860700013|376014; X-Microsoft-Antispam-Message-Info: UHpOiwgRe6FxkV1ExtxtDm0ui3D2bCczv8ZXlNg6c3yJRZlfKbpxYSIGNkvqzWusS/QxFhkxTZvOQvdlU4LySssBmV8VenXhHB/bG5nUcQXIaFNDC9EnBWQoMVZ1wpAuUOSuj+1axhoSYK9x33BMmrlVghwuJVXTlQgqmEt1jjes215oVzmVlRU+JmOiWFbtscJl35xRGEK0O/bGVfP6XS7bNnSDlUI2mRQIyCWr+nQk9e2UuXgHsSO7zVAtXSD/8bQh1XYl2HGlE5DJ3lHu+4JOS8mFnxFFVXHAH7s+bd3HRUj4JYp0U0v29j+9DztKiIBZPlNct6adeshdxOnrlXE4uxhUS3N/Sjmg2pr99RSENE+JbZkG/D4mAj8MoYsRYOpnUejl+dsFQpXvb/YKM9uTjVfKykIdVKa32rbcoIWhhdCwoFuq3v5WafEBrFw2KhNWlRtSSBe0ndgguwt58hyUQn0xhrtlfKR6ASRz6kSRoybEcuM/GZl76umLkRMvwDbr4lE3YS8oo9+U4NQ2g8gvhtz8V6kquegOjRhjSstd81FYtsosSyZtOlfO7lpwjnQm7ZbVrN6gh/1IUvEfJ6AiLq11cxpPO0zt2XDN41tohhWkrmhDlhyfL+6DefMnzGGvfI4bloZFQheDHlSMKl+D3v+ULQTMF7uLawXVSUi0hyvhukA2icdR93E1FIKQSXwJhfQYRLzxyfGEwDSBCAwptVCBQ30hxzU7X1GAnWWtOJshl7ETAUjnGGonmRamuspYHV7QSY6bF54f+/2+xs+RtA3ET9OG/mb4Hnzw1NIE+Ww+k2phgfKf1mypfaRIGxWu45Wk7KteaN8ytAIriIGg7yqbLPi2jUn0d9F4Uwy7sq9xQajswe1cwGMcDFxO6FYKevxDZd03juqwTC+h7K4yrP66F6YNyiObDvMwM5TMP3+7KiTcRaxYa8zpuX0/BiLinjek2nvqkqwg+B6VK8uNQASN0WmVUvcFuqwL57dL9F+5+DNuQ5kOsMMsFEueFwmft6GNo+rLm1lVc1tlCmu3UsCRvS24hPSgvUBiYUealKiIu1y8RogHprb24ajQs54svPn/h2h053LwBSjAqOBpdRzlI7AiJsRPsqXxcbT90A4qkEHvxHbEs0WTjS/bt1yvWYvYL0Ky5DWCn47oaXhKvGFfWxam5RBAPWYpDE51TkVXDhO0LdyXbaOmwIDo/0AfKRsOZYgso7dH6ef3RT/c8q+6HaIc1e1zDBIrUbh/icz0DWQAnSRimbiBrZoO7dKSEhZoR4oq5GR804Red4GthJsNcgxA8rMe4TcbtMRm3Nm3fWKqg1BZAW+1poKFnujVHIhBbEJdz7591pOM8uzSVQVJjDEefqGsZTRdrrgrleyqSAau7S3/bfIuegY1nmScIgYKZ7lQeID50eRps6B9FW7JsBLASXm+L0YJf5ZNpyITS+70yITsbAXtPX0J X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(7416014)(36860700013)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Nov 2024 14:07:44.4742 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8ce1e6fd-8163-43a9-612c-08dd11485c9e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9339 From: Perry Yuan Introduces new MSR registers for AMD hardware feedback support. These registers enable the system to provide workload classification and configuration capabilities. Reviewed-by: Gautham R. Shenoy Signed-off-by: Perry Yuan Signed-off-by: Mario Limonciello --- arch/x86/include/asm/msr-index.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 3ae84c3b8e6db..0cd5ffe50f4a4 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -712,6 +712,11 @@ #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 +/* AMD Hardware Feedback Support MSRs */ +#define AMD_WORKLOAD_CLASS_CONFIG 0xc0000500 +#define AMD_WORKLOAD_CLASS_ID 0xc0000501 +#define AMD_WORKLOAD_HRST 0xc0000502 + /* AMD Last Branch Record MSRs */ #define MSR_AMD64_LBR_SELECT 0xc000010e