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Peter Anvin" , "Rafael J . Wysocki" , "Gautham R . Shenoy" , Mario Limonciello , Perry Yuan , Brijesh Singh , Peter Zijlstra , Li RongQing , "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "open list:ACPI" , "open list:AMD PSTATE DRIVER" , Pawan Gupta Subject: [PATCH v3 5/5] x86/amd: Use heterogeneous core topology for identifying boost numerator Date: Wed, 23 Oct 2024 12:43:57 -0500 Message-ID: <20241023174357.34338-6-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241023174357.34338-1-mario.limonciello@amd.com> References: <20241023174357.34338-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CE:EE_|MN2PR12MB4222:EE_ X-MS-Office365-Filtering-Correlation-Id: 972544a5-42ab-4bd0-a555-08dcf38a615e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|7416014|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: MsIQymDLo3U7hjHcrAso1uy/yUQICFGqa3PPbJTTnmwAOjdpt5Hn0F/Q2CDU6gMStnSmZh9NEIHtrbGicMs6zNHzCOJgyrw0pLAZ+b50PauJqn59xgY4gX2PND7snfQih9dlKXxVisVTj75QrgHFSRB7Z76AWOnPn3T/JnrapLHZ9/htyVcQYKKy5hm8fcxsB0V0lxzXUxo2ofIXAysnOPV5t3H2wNzj2u/G7t1/yRotsHhCC64UjR6qqoKBwuk+e0S4WMjxpcCdcuk1ISqbDDscxKtfenMH7VI4BcY67hZ8xQu9YaI9mpMO2mohWh4RDWqbXVOblnrjF6JjPL8fAxFVjlW25gzuxCWOuD9koJXatLm174oKmztp1bmESRKHy2AdtzzQbePzpIcO79RCwP384x/RQdlMyllIAkPlTqaRejJGbZeBDZUBBgblI86lmxSfOjgZ6o5jSKW/MQ/qy5pPQqfLJA1Z1cxhcqc8YPk+NHIvnQtXg4pHHfyfi8dQsOLFuUtwmRMpaKGO/KQPExQDmySq1ov0eQ6cjBuMNFxeUqsSgO0CUcVe2TrXjMUKOlDRmD6rAXuZ6hof/ILCG25Omk6nt3rA7v2iG60aLyvT/Cjr6pVt27IWm3JElC+dK92/49tFb/4Vc83M1OthoH0JpDFVAL7ZLMi6/0inUDadA6fX0Vgx34W+o/qC/5D6aXPEHMlKe+fCBpFzj7IyVHMO6gqczCzz/2AH/85erIvSXsNQqg8jGPyknHyreLIQZpJ7rNkV83rtxPQtHf7dNGxBCHsO5wn7Y712S8UNud8a3/2gkG5Kr0KBpS8Q9hhGwg7vAOK9ot8kdk51mAEHfuYZ8HZXYmpdNcNnKqhpaKtXCEAs7s6IJvmHYd2uf5q6wQCOk2+fGKizXSDhHURPYMyqI0GErbQNMPlSXSqs2Ne8mwuBLRYlwQXF0wNwZcAAcWn/M2iQU+KXgC6sThrbtrrGiIKI9rYmGPC4y46Hov3zRtMxS/PsXoGZ/rNzwO2T2IVw4X09KaLu365qDBb6MUKW/XPBbB7bDuEge6yopJveQu6sEGa3VDTLQo60kZ/6FIVwKEN9EubQB+jnkDKYIpaJ9rR51d2sVE3zdADAp5Kv6ugovuLB86/BfHZPk4qoMEw5k/z/EPCvxNcE/wfJMBDzJewRR1m14Q6EEeI7tQSoNOPFf4QBeLMUqfD8i5evgsb6+GiWzKFNEmiskm5nYHGLK+zuvHqDuDlmx8gRmUFT4eDt7VctWKCMI2OBSPAXzp3usypw2gtMOW75WeaZMiRzxpst3IimvQ1M159vPZOTByQByD3JtwsUPCx8ZXXpdRN+OJVwxIzqVxE2uEzA1Z+NuvJ1bDHwbfRwLrv57qjNpoomDDTmVhSJ0W86o7/wK2lKGQGEOuCj+M/hC8DXzw== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(7416014)(376014)(36860700013)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 17:44:44.2678 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 972544a5-42ab-4bd0-a555-08dcf38a615e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4222 AMD heterogeneous designs include two types of cores: * Performance * Efficiency Each core type has different highest performance values configured by the platform. Drivers such as `amd_pstate` need to identify the type of core to correctly set an appropriate boost numerator to calculate the maximum frequency. X86_FEATURE_AMD_HETEROGENEOUS_CORES is used to identify whether the SoC supports heterogeneous core type by reading CPUID leaf Fn_0x80000026. On performance cores the scaling factor of 196 is used. On efficiency cores the scaling factor is the value reported as the highest perf. Efficiency cores have the same preferred core rankings. Suggested-by: Perry Yuan Signed-off-by: Mario Limonciello --- arch/x86/kernel/acpi/cppc.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c index 956984054bf30..9983d4537968f 100644 --- a/arch/x86/kernel/acpi/cppc.c +++ b/arch/x86/kernel/acpi/cppc.c @@ -234,8 +234,10 @@ EXPORT_SYMBOL_GPL(amd_detect_prefcore); */ int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator) { + enum x86_topology_cpu_type core_type = get_topology_generic_cpu_type(&cpu_data(cpu)); bool prefcore; int ret; + u32 tmp; ret = amd_detect_prefcore(&prefcore); if (ret) @@ -261,6 +263,27 @@ int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator) break; } } + + /* detect if running on heterogeneous design */ + switch (core_type) { + case TOPO_CPU_TYPE_UNKNOWN: + break; + case TOPO_CPU_TYPE_PERFORMANCE: + /* use the max scale for performance cores */ + *numerator = CPPC_HIGHEST_PERF_PERFORMANCE; + return 0; + case TOPO_CPU_TYPE_EFFICIENCY: + /* use the highest perf value for efficiency cores */ + ret = amd_get_highest_perf(cpu, &tmp); + if (ret) + return ret; + *numerator = tmp; + return 0; + default: + pr_warn("WARNING: Undefined core type %d found\n", core_type); + break; + } + *numerator = CPPC_HIGHEST_PERF_PREFCORE; return 0;