[RFC,1/6] ACPICA: actbl1.h: Add extended linear address mode to MSCIS

ECN for "Extended-linear" addressing for direct-mapped memory-side caches
adds a field in the SRAT Memory Side CAche Information Structure to
indicate the address mode at the previously reserved bytes at offset 28.

The field is described as:
When Address Mode is 1 'Extended-Linear' it indicates that the
associated address range (SRAT.MemoryAffinityStructure.Length) is
comprised of the backing store capacity extended by the cache
capacity. It is arranged such that there are N directly addressable
aliases of a given cacheline where N is an integer ratio of target memory
proximity domain size and the memory side cache size. Where the N
aliased addresses for a given cacheline all share the same result
for the operation 'address modulo cache size'. This setting is only
allowed when 'Cache Associativity' is 'Direct Map'."

Link: https://lore.kernel.org/linux-cxl/668333b17e4b2_5639294fd@dwillia2-xfh.jf.intel.com.notmuch/
Link: https://github.com/acpica/acpica/pull/961
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
---
 include/acpi/actbl1.h | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

On Fri, Sep 27, 2024 at 4:21 PM Dave Jiang <dave.jiang@intel.com> wrote:
>
> ECN for "Extended-linear" addressing for direct-mapped memory-side caches
> adds a field in the SRAT Memory Side CAche Information Structure to
> indicate the address mode at the previously reserved bytes at offset 28.
>
> The field is described as:
> When Address Mode is 1 'Extended-Linear' it indicates that the
> associated address range (SRAT.MemoryAffinityStructure.Length) is
> comprised of the backing store capacity extended by the cache
> capacity. It is arranged such that there are N directly addressable
> aliases of a given cacheline where N is an integer ratio of target memory
> proximity domain size and the memory side cache size. Where the N
> aliased addresses for a given cacheline all share the same result
> for the operation 'address modulo cache size'. This setting is only
> allowed when 'Cache Associativity' is 'Direct Map'."
>
> Link: https://lore.kernel.org/linux-cxl/668333b17e4b2_5639294fd@dwillia2-xfh.jf.intel.com.notmuch/
> Link: https://github.com/acpica/acpica/pull/961

This pull request has been merged into upstream ACPICA, so

Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

and I'm assuming that it will be routed through the CXL tree along
with the rest of the patch series.

Thanks!

> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> ---
>  include/acpi/actbl1.h | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
> index 841ef9f22795..95ddc858a0c3 100644
> --- a/include/acpi/actbl1.h
> +++ b/include/acpi/actbl1.h
> @@ -1791,7 +1791,7 @@ struct acpi_hmat_cache {
>         u32 reserved1;
>         u64 cache_size;
>         u32 cache_attributes;
> -       u16 reserved2;
> +       u16 address_mode;
>         u16 number_of_SMBIOShandles;
>  };
>
> @@ -1803,6 +1803,9 @@ struct acpi_hmat_cache {
>  #define ACPI_HMAT_WRITE_POLICY          (0x0000F000)
>  #define ACPI_HMAT_CACHE_LINE_SIZE       (0xFFFF0000)
>
> +#define ACPI_HMAT_CACHE_MODE_UNKNOWN           (0)
> +#define ACPI_HMAT_CACHE_MODE_EXTENDED_LINEAR   (1)
> +
>  /* Values for cache associativity flag */
>
>  #define ACPI_HMAT_CA_NONE                     (0)
> --
> 2.46.1
>