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Wysocki" , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , =?utf-8?q?P?= =?utf-8?q?ali_Roh=C3=A1r?= , =?utf-8?q?Marek_Beh=C3=BAn?= , "Maciej W . Rozycki" , Manivannan Sadhasivam , Mario Limonciello , "open list:DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS" , "open list:DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS" , "open list" , "open list:RADEON and AMDGPU DRM DRIVERS" , "open list:PCI SUBSYSTEM" , "open list:ACPI" Subject: [PATCH v3 6/7] PCI: Split up some logic in pcie_bandwidth_available() to separate function Date: Tue, 14 Nov 2023 14:07:54 -0600 Message-ID: <20231114200755.14911-7-mario.limonciello@amd.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231114200755.14911-1-mario.limonciello@amd.com> References: <20231114200755.14911-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A103:EE_|DS7PR12MB5720:EE_ X-MS-Office365-Filtering-Correlation-Id: 17897260-4f72-446a-fd65-08dbe54d7d33 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HdIL6B+xxFbeG2i6btoJu2mwGxAav6nSk9t9VHeCYelwn0IODKr9Ff59Js4BaBOY88tL8nkrtJlBgOvsG6LdApVU4jlXCkcCLQOUdoWkDOG1LnvMGWX2/XtgYMtotvMieAiEKVrO6bofQ4tpAVVIw0vtFnC80DG4P/+4+rF8/jV3iKNla3yxtOEOikzTpa4ukx2kiMG1qRSbKlUTqTCD4xBrUtEQ4yaB1FnYcxYtfcnBcpnktgtyC584O4oB/KrqAQdRUGMefZf4jD3otLOOYNEIjLWN5oOyhPLaJXo6GAeWsX8pivVZwZCtzJwH30+dbRbyoik38Frspu9GJnDR01VIC73WJHYxlnyvYbARgd2bp/nET/Xg/oIY3jJqnYM8/Y+00GPa+KgRDenMyyOTR5CDWehLlhlHskDWIRD6hQDXh6Jaeb47Xj59X5+wmfCaO0801/xurYkP3I6uOWgWiurQnH/kFD5S8av2Y/RHmu/J48vWTB0mcpFryD+dArhZUFYCTSHyfMelVjvPdiEe6RBSAMXucZDPd+YSd00aqBO2NpOR8aDop5IYlfdG8yG0bRLC0bRmLbvTGHUBQsWB2hQHrkBpzVyGf7OdEicrphEWNgUZzyINTGhISwaVn/OuK4AP5fWZByyOEHX78J+Ett1CRKPyxn/T1EkGQuABLvQHUaGSYJswS7rN45NrhXIm8Pt5zq+QcO8BGs2fcxxU2RR25gmzmN74OBQSBohEeDRhMUnvGOgipfa6qPR32hzDoBFfItfZJOPityWVicSNJg== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(396003)(136003)(376002)(39860400002)(346002)(230922051799003)(1800799009)(82310400011)(64100799003)(186009)(451199024)(36840700001)(40470700004)(46966006)(40480700001)(426003)(40460700003)(316002)(70586007)(110136005)(70206006)(54906003)(81166007)(26005)(356005)(82740400003)(86362001)(36756003)(83380400001)(336012)(1076003)(6666004)(16526019)(2616005)(36860700001)(478600001)(2906002)(7696005)(47076005)(5660300002)(44832011)(41300700001)(4326008)(8676002)(7416002)(8936002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Nov 2023 20:08:37.7140 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 17897260-4f72-446a-fd65-08dbe54d7d33 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A103.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5720 The logic to calculate bandwidth limits may be used at multiple call sites so split it up into its own static function instead. No intended functional changes. Suggested-by: Ilpo Järvinen Signed-off-by: Mario Limonciello Reviewed-by: Ilpo Järvinen --- v2->v3: * Split from previous patch version --- drivers/pci/pci.c | 60 +++++++++++++++++++++++++++-------------------- 1 file changed, 34 insertions(+), 26 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 55bc3576a985..0ff7883cc774 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -6224,6 +6224,38 @@ int pcie_set_mps(struct pci_dev *dev, int mps) } EXPORT_SYMBOL(pcie_set_mps); +static u32 pcie_calc_bw_limits(struct pci_dev *dev, u32 bw, + struct pci_dev **limiting_dev, + enum pci_bus_speed *speed, + enum pcie_link_width *width) +{ + enum pcie_link_width next_width; + enum pci_bus_speed next_speed; + u32 next_bw; + u16 lnksta; + + pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); + + next_speed = pcie_link_speed[FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta)]; + next_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta); + + next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed); + + /* Check if current device limits the total bandwidth */ + if (!bw || next_bw <= bw) { + bw = next_bw; + + if (limiting_dev) + *limiting_dev = dev; + if (speed) + *speed = next_speed; + if (width) + *width = next_width; + } + + return bw; +} + /** * pcie_bandwidth_available - determine minimum link settings of a PCIe * device and its bandwidth limitation @@ -6242,39 +6274,15 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, enum pci_bus_speed *speed, enum pcie_link_width *width) { - u16 lnksta; - enum pci_bus_speed next_speed; - enum pcie_link_width next_width; - u32 bw, next_bw; + u32 bw = 0; if (speed) *speed = PCI_SPEED_UNKNOWN; if (width) *width = PCIE_LNK_WIDTH_UNKNOWN; - bw = 0; - while (dev) { - pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); - - next_speed = pcie_link_speed[FIELD_GET(PCI_EXP_LNKSTA_CLS, - lnksta)]; - next_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta); - - next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed); - - /* Check if current device limits the total bandwidth */ - if (!bw || next_bw <= bw) { - bw = next_bw; - - if (limiting_dev) - *limiting_dev = dev; - if (speed) - *speed = next_speed; - if (width) - *width = next_width; - } - + bw = pcie_calc_bw_limits(dev, bw, limiting_dev, speed, width); dev = pci_upstream_bridge(dev); }