From patchwork Wed Apr 5 09:27:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marco Felsch X-Patchwork-Id: 670420 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01D87C7619A for ; Wed, 5 Apr 2023 09:30:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237671AbjDEJa3 (ORCPT ); Wed, 5 Apr 2023 05:30:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237743AbjDEJ35 (ORCPT ); Wed, 5 Apr 2023 05:29:57 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B1835258 for ; Wed, 5 Apr 2023 02:29:29 -0700 (PDT) Received: from dude02.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::28]) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1pjzQB-0004pA-3d; Wed, 05 Apr 2023 11:27:15 +0200 From: Marco Felsch Date: Wed, 05 Apr 2023 11:27:03 +0200 Subject: [PATCH 12/12] net: phy: add default gpio assert/deassert delay MIME-Version: 1.0 Message-Id: <20230405-net-next-topic-net-phy-reset-v1-12-7e5329f08002@pengutronix.de> References: <20230405-net-next-topic-net-phy-reset-v1-0-7e5329f08002@pengutronix.de> In-Reply-To: <20230405-net-next-topic-net-phy-reset-v1-0-7e5329f08002@pengutronix.de> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Florian Fainelli , Broadcom internal kernel review list , Richard Cochran , Radu Pirea , Shyam Sundar S K , Yisen Zhuang , Salil Mehta , Jassi Brar , Ilias Apalodimas , Iyappan Subramanian , Keyur Chudgar , Quan Nguyen , "Rafael J. Wysocki" , Len Brown , Rob Herring , Frank Rowand Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, devicetree@vger.kernel.org, kernel@pengutronix.de X-Mailer: b4 0.12.1 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::28 X-SA-Exim-Mail-From: m.felsch@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-acpi@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org There are phy's not mention any assert/deassert delay within their datasheets but the real world showed that this is not true. They need at least a few us to be accessible and to readout the register values. So add a sane default value of 1000us for both assert and deassert to fix this in a global matter. Signed-off-by: Marco Felsch --- drivers/net/phy/phy_device.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 30b3ac9818b1..08f2657110e0 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -3197,6 +3197,9 @@ fwnode_find_mii_timestamper(struct fwnode_handle *fwnode) return register_mii_timestamper(arg.np, arg.args[0]); } +#define DEFAULT_GPIO_RESET_ASSERT_DELAY_US 1000 +#define DEFAULT_GPIO_RESET_DEASSERT_DELAY_US 1000 + static int phy_device_parse_fwnode(struct phy_device *phydev, struct phy_device_config *config) @@ -3223,8 +3226,11 @@ phy_device_parse_fwnode(struct phy_device *phydev, if (fwnode_property_read_bool(fwnode, "broken-turn-around")) bus->phy_ignore_ta_mask |= 1 << addr; + + phydev->mdio.reset_assert_delay = DEFAULT_GPIO_RESET_ASSERT_DELAY_US; fwnode_property_read_u32(fwnode, "reset-assert-us", &phydev->mdio.reset_assert_delay); + phydev->mdio.reset_deassert_delay = DEFAULT_GPIO_RESET_DEASSERT_DELAY_US; fwnode_property_read_u32(fwnode, "reset-deassert-us", &phydev->mdio.reset_deassert_delay);