From patchwork Fri Mar 3 13:36:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 658495 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0008C7EE2F for ; Fri, 3 Mar 2023 13:38:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231314AbjCCNiS (ORCPT ); Fri, 3 Mar 2023 08:38:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231240AbjCCNhv (ORCPT ); Fri, 3 Mar 2023 08:37:51 -0500 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D781260D66 for ; Fri, 3 Mar 2023 05:37:29 -0800 (PST) Received: by mail-pj1-x102f.google.com with SMTP id bo22so2513832pjb.4 for ; Fri, 03 Mar 2023 05:37:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1677850649; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mBemuZ+2YkCjmi93Yb84bL6oYK/bVtvUR58SW7DcwbA=; b=eYfH8EfFgcshApQyiD3xCOf6+OIvUW8qg/k65nzJniZ/k9eVqQDqG4PbYKxUTWA/9W Auo7twOv5LJOHiXqBtC8Ig76Sh/WrEIqXL0PV4G2LCXte845FsmbU+aJK9gn2RTneuw+ 3KmPv1uXHl3IhytdLToTKGF6DqkpUKH8RpMVMn5FWXldGuUrRVv8mJ4+W4rPVlgs4ymw C6GwEmhJsRMjpGxHk29vSP72+mRzMZhTomILvoRtKDfsOQarwqiewo3PZ2m5s3njvp6w P1v+7XeYAu8kBDoikWbO3+jIBxxJrYOzyGCCBkA+AroMdTv3B2FvCRGth7xpdO+A0/ca YN2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677850649; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mBemuZ+2YkCjmi93Yb84bL6oYK/bVtvUR58SW7DcwbA=; b=PUo/HabDIrpGaem4/uViMUbohbS8YSjMH68glkZJOQ8rKGjNIEY73Df2X9qIez2Nky GwXVjjuKPa5PhwO4jKYaKsigNonp4PZRlCPWTDN+O/6oyG8IVCmJyJ7GKZN5qoei6Ut0 j3PGCm10d4VpvuWIP5vuvqnDs2zvN7r0a2ZKY1aqFnVNtPmqgTHWjlFOu/9qG2ut6sD/ t0Hxk9uey6EHz3sEAHFroY3y2T2rHa++s2Kf3KleNoL8glmQ39DPSpiYgXVBKokju5FY 8TXgErltQST/qZxOZAzjJI56qEQdm3IBA4qxzB5i/Lv+NK46tYUaNH5GA51hCUYM/X5F TSqQ== X-Gm-Message-State: AO0yUKUCz1nI8X5kq4x2fbcbumDnVLApUVAmIocHWWu5yGl2JQFP04I/ PDPDV0HBVXrnVDVGlFEPPeXzZQ== X-Google-Smtp-Source: AK7set9oosEAFz5om7ghzkTjM/ikMsO16Y20aDm8j/67h0FEs1pP70F94+f/EPbTvvbSLSV8NQGNjQ== X-Received: by 2002:a17:902:d2c9:b0:19a:7d0e:ceea with SMTP id n9-20020a170902d2c900b0019a7d0eceeamr1996033plc.25.1677850649367; Fri, 03 Mar 2023 05:37:29 -0800 (PST) Received: from localhost.localdomain ([49.206.14.226]) by smtp.gmail.com with ESMTPSA id m9-20020a170902768900b0019ac5d3ee9dsm1533125pll.157.2023.03.03.05.37.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Mar 2023 05:37:29 -0800 (PST) From: Sunil V L To: linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Cc: Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Andrew Jones , Atish Patra , 'Conor Dooley ' , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V3 07/20] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid Date: Fri, 3 Mar 2023 19:06:34 +0530 Message-Id: <20230303133647.845095-8-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org processor_core needs arch-specific functions to map the ACPI ID to the physical ID. In RISC-V platforms, hartid is the physical id and RINTC structure in MADT provides this mapping. Add arch-specific function to get this mapping from RINTC. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones --- arch/riscv/include/asm/acpi.h | 3 +++ drivers/acpi/processor_core.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 0b52a190f71a..7671c401f4ec 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -15,6 +15,9 @@ /* Basic configuration for ACPI */ #ifdef CONFIG_ACPI +typedef u64 phys_cpuid_t; +#define PHYS_CPUID_INVALID INVALID_HARTID + /* ACPI table mapping after acpi_permanent_mmap is set */ void *acpi_os_ioremap(acpi_physical_address phys, acpi_size size); #define acpi_os_ioremap acpi_os_ioremap diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c index 2ac48cda5b20..d6606a9f2da6 100644 --- a/drivers/acpi/processor_core.c +++ b/drivers/acpi/processor_core.c @@ -106,6 +106,32 @@ static int map_gicc_mpidr(struct acpi_subtable_header *entry, return -EINVAL; } +/* + * Retrieve the RISC-V hartid for the processor + */ +static int map_rintc_hartid(struct acpi_subtable_header *entry, + int device_declaration, u32 acpi_id, + phys_cpuid_t *hartid) +{ + struct acpi_madt_rintc *rintc = + container_of(entry, struct acpi_madt_rintc, header); + + if (!(rintc->flags & ACPI_MADT_ENABLED)) + return -ENODEV; + + /* device_declaration means Device object in DSDT, in the + * RISC-V, logical processors are required to + * have a Processor Device object in the DSDT, so we should + * check device_declaration here + */ + if (device_declaration && rintc->uid == acpi_id) { + *hartid = rintc->hart_id; + return 0; + } + + return -EINVAL; +} + static phys_cpuid_t map_madt_entry(struct acpi_table_madt *madt, int type, u32 acpi_id) { @@ -136,6 +162,9 @@ static phys_cpuid_t map_madt_entry(struct acpi_table_madt *madt, } else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT) { if (!map_gicc_mpidr(header, type, acpi_id, &phys_id)) break; + } else if (header->type == ACPI_MADT_TYPE_RINTC) { + if (!map_rintc_hartid(header, type, acpi_id, &phys_id)) + break; } entry += header->length; }