From patchwork Thu Aug 5 08:07:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 492246 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:396:0:0:0:0 with SMTP id y22csp55573jap; Thu, 5 Aug 2021 01:09:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzlZCfw1fSx3khcnCq9qR02gzzwuWUHxareB3lOV4iODg681l9YMyDbxI9nB7BCjsFDs8x9 X-Received: by 2002:a17:906:a04f:: with SMTP id bg15mr3668920ejb.417.1628150974485; Thu, 05 Aug 2021 01:09:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1628150974; cv=none; d=google.com; s=arc-20160816; b=C7aRcduatTMzkQkUVgl7pr31C3GJF5aJOVcDvBcv1VjCyd8H5q7ghMcjgnQ0QbM85Q OSm7Eus+wqy52pTPEKe4OwbL481Vh4BwKALhldiEPDR+bAU9Az/nwtrA/NVtMMQ8+Mvw 05D4frXSO8IHzxsmeCCoeBt6TaCXdbQM21IlT82d9xRvo4jhLOSFIvN6UQVSuVwX+LCZ gUB+PXb9QJaPxZc/zDGeW2iWMXRFYZ7WDDz1cnGzA8TVQc3BQTIyOMVjYF9qi2bdSLhc xiOJoWQF/gDfzO19727hDH1bqoWH4+yurkFlwF3Art4HTI4AZSnJQJtkhr9YNVpEtmNu lAPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=P6h8VURn8a2xqvzxeDK3AvXzvUWTuF93ZASR46rodpk=; b=zebox5tWHWymWKRUkhC87Bjvg02qXifLZ3vkuDEFG2jbm6jRGDtInd6tb1+n34atUI yy3O76fF94y+BWxeRIAmPm7uzI6o8XgdY53/ALte0dKbipV4Y0vKbeO9JqCpXIIyiDpw 0MH1OtLiFSKm8ZMZgki8XZ/IvBHNHN8B1AocqaPyWsBmIrHcwXnPO8jmQLor4jcgBGJk nC0kAmsEc6KwRvf5gnD+/IDYtmtWmFwg8ad+F0SNRcyJksEC3I49pFq49ohjRpv/uGfz xJ/q6QVInaoHg+4SB7Iw3fmdIdeL2mjFWZe3+wQSRmMjWEjdCUUeFgk5Nq9DAdbdbg/f Ewuw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-acpi-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=huawei.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id g18si5224762ejp.458.2021.08.05.01.09.34; Thu, 05 Aug 2021 01:09:34 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-acpi-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-acpi-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=huawei.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234289AbhHEIJr (ORCPT + 4 others); Thu, 5 Aug 2021 04:09:47 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]:3590 "EHLO frasgout.his.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233484AbhHEIJq (ORCPT ); Thu, 5 Aug 2021 04:09:46 -0400 Received: from fraeml736-chm.china.huawei.com (unknown [172.18.147.201]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4GgLqG2lZkz6F8Fl; Thu, 5 Aug 2021 16:09:14 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml736-chm.china.huawei.com (10.206.15.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 5 Aug 2021 10:09:31 +0200 Received: from A2006125610.china.huawei.com (10.47.91.4) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 5 Aug 2021 09:09:24 +0100 From: Shameer Kolothum To: , , CC: , , , , , , , , , , , Subject: [PATCH v7 6/9] =?utf-8?q?iommu/arm-smmu-v3=3A_Refactor=C2=A0arm?= =?utf-8?q?=5Fsmmu=5Finit=5Fbypass=5Fstes=28=29_to_force_bypass?= Date: Thu, 5 Aug 2021 09:07:21 +0100 Message-ID: <20210805080724.480-7-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20210805080724.480-1-shameerali.kolothum.thodi@huawei.com> References: <20210805080724.480-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.91.4] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org By default, disable_bypass flag is set and any dev without an iommu domain installs STE with CFG_ABORT during arm_smmu_init_bypass_stes(). Introduce a "force" flag and move the STE update logic to arm_smmu_init_bypass_stes() so that we can force it to install CFG_BYPASS STE for specific SIDs. This will be useful in follow-up patch to install bypass for IORT RMR SIDs. Signed-off-by: Shameer Kolothum --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 31940e53c675..85f6f1925a36 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1357,12 +1357,21 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd); } -static void arm_smmu_init_bypass_stes(__le64 *strtab, unsigned int nent) +static void arm_smmu_init_bypass_stes(__le64 *strtab, unsigned int nent, bool force) { unsigned int i; + u64 val = STRTAB_STE_0_V; + + if (disable_bypass && !force) + val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT); + else + val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS); for (i = 0; i < nent; ++i) { - arm_smmu_write_strtab_ent(NULL, -1, strtab); + strtab[0] = cpu_to_le64(val); + strtab[1] = cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG, + STRTAB_STE_1_SHCFG_INCOMING)); + strtab[2] = 0; strtab += STRTAB_STE_DWORDS; } } @@ -1390,7 +1399,7 @@ static int arm_smmu_init_l2_strtab(struct arm_smmu_device *smmu, u32 sid) return -ENOMEM; } - arm_smmu_init_bypass_stes(desc->l2ptr, 1 << STRTAB_SPLIT); + arm_smmu_init_bypass_stes(desc->l2ptr, 1 << STRTAB_SPLIT, false); arm_smmu_write_strtab_l1_desc(strtab, desc); return 0; } @@ -3042,7 +3051,7 @@ static int arm_smmu_init_strtab_linear(struct arm_smmu_device *smmu) reg |= FIELD_PREP(STRTAB_BASE_CFG_LOG2SIZE, smmu->sid_bits); cfg->strtab_base_cfg = reg; - arm_smmu_init_bypass_stes(strtab, cfg->num_l1_ents); + arm_smmu_init_bypass_stes(strtab, cfg->num_l1_ents, false); return 0; }