From patchwork Thu May 13 13:45:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 437331 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp345692jao; Thu, 13 May 2021 06:47:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzstexDQVYQNIJ6GyxpTeMBuq+3jSRP0FkmGL7X2i1k6eAt+Ldyn1fUzbLflYtEBQmWHE7H X-Received: by 2002:a05:6e02:12:: with SMTP id h18mr37230377ilr.246.1620913624419; Thu, 13 May 2021 06:47:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620913624; cv=none; d=google.com; s=arc-20160816; b=R3FAZFslEeHmziQWeoI2wY/KJaojh75fnjyX5Mg2aGFBIlsmFFEsZowbzOXBlzykOy APq5TUPnNkbk3y2UwsIEAe6pf6ce6LT/Aby9unarnHlpukGD/cq8m7pgjzS3kmfox+3P PdJiz2qzAwr1XB+PjSkvJTdTRKUCIr6pjM3uDYZMEcb3OucK894TE69nosQ3eyJArUcB 7/EfTipsMiOXJwIzbXO7URM4kTkTKXGYpNkPrinVdTLeQZqJMQXULBOGlGnhjkgGDnPb kssHhOQy3p7X2lbBLLxUj+SbRRaHF/tDX5RpoMiSExEXG8q3hg3+uq2VG/7XNBGN3D5m WCMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=dLcifpRbpGOOo5l2uyzsGI7847e1bclNUfLumTjbuCo=; b=a7rUP8EZD4kn4bs5B3fb3lZIrmTkqLvYGcEu0EqwQssSaZJ5Ir+Fb3bNAI4ibno0/u 4+9QKqEKjXYTwvjL7R7lCsn/IKf2HbS5+96avvp6oCZVvtStb+G8cgwOnbY6+oG7RzUz dgseErZNaMn61FXmdQRHt2T5UkA0P783IQtO7ERTrNSL9zusTmLJWVtRGij+S81rgDMY vQhL6oEhfJZcUpXZ1TURIyiLbbboNpvzAnC8snCzMAHk0LMcaYwWl2OD9zeM2QuFbcwn 23TYI6eqbwNIxZu32Xpi917RmgKGheUvSdIrg2ZenX6wM2708YaT9moW5UF6fjUgB9nX b15w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-acpi-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=huawei.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id u10si3346494ilv.5.2021.05.13.06.47.04; Thu, 13 May 2021 06:47:04 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-acpi-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-acpi-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=huawei.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234135AbhEMNsK (ORCPT + 4 others); Thu, 13 May 2021 09:48:10 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:2724 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234047AbhEMNsF (ORCPT ); Thu, 13 May 2021 09:48:05 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4FgtDY1Rg6z16LjG; Thu, 13 May 2021 21:44:13 +0800 (CST) Received: from A2006125610.china.huawei.com (10.47.81.63) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.498.0; Thu, 13 May 2021 21:46:47 +0800 From: Shameer Kolothum To: , , CC: , , , , , , , , , , Subject: [PATCH v4 5/8] =?utf-8?q?iommu/arm-smmu-v3=3A_Add_bypass_flag_to?= =?utf-8?b?wqBhcm1fc21tdV93cml0ZV9zdHJ0YWJfZW50KCk=?= Date: Thu, 13 May 2021 14:45:47 +0100 Message-ID: <20210513134550.2117-6-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20210513134550.2117-1-shameerali.kolothum.thodi@huawei.com> References: <20210513134550.2117-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.81.63] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org By default, disable_bypass is set and any dev without an iommu domain installs STE with CFG_ABORT during arm_smmu_init_bypass_stes(). Introduce a "bypass" flag to arm_smmu_write_strtab_ent() so that we can force it to install CFG_BYPASS STE for specific SIDs. This will be useful in follow up patch to install bypass for IORT RMR SIDs. Signed-off-by: Shameer Kolothum --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 754bad6092c1..f9195b740f48 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1174,7 +1174,7 @@ static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid) } static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, - __le64 *dst) + __le64 *dst, bool bypass) { /* * This is hideously complicated, but we only really care about @@ -1245,7 +1245,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, /* Bypass/fault */ if (!smmu_domain || !(s1_cfg || s2_cfg)) { - if (!smmu_domain && disable_bypass) + if (!smmu_domain && disable_bypass && !bypass) val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT); else val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS); @@ -1320,7 +1320,7 @@ static void arm_smmu_init_bypass_stes(__le64 *strtab, unsigned int nent) unsigned int i; for (i = 0; i < nent; ++i) { - arm_smmu_write_strtab_ent(NULL, -1, strtab); + arm_smmu_write_strtab_ent(NULL, -1, strtab, false); strtab += STRTAB_STE_DWORDS; } } @@ -2097,7 +2097,7 @@ static void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master) if (j < i) continue; - arm_smmu_write_strtab_ent(master, sid, step); + arm_smmu_write_strtab_ent(master, sid, step, false); } }