From patchwork Tue Apr 20 08:27:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 424560 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp206895jao; Tue, 20 Apr 2021 02:29:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy82v4MCDSCWlC7xM8lLPjOTHoD+jX2jVCmZkvmzQCI7oQ/TOP7fv79N7rP8QdtAZ5dG6WR X-Received: by 2002:a17:906:29ca:: with SMTP id y10mr27301622eje.250.1618910939899; Tue, 20 Apr 2021 02:28:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618910939; cv=none; d=google.com; s=arc-20160816; b=a9Aa2tGRbgVccVbHCjw1QlLJFpZtLRLuqPmJR569YzCKq056nIRrlU+rYNtGSQa+bg buY5OBIogeoOVzGvcKhhWRVYjLqsZOOdALUllR2LESMweJaK5VrAldv9W84kGR3UA7p2 tNzMSX4Kl2VjJm02iVf8787bEtN20BFfq8vJeQ5PsVaa39dwPuowBeRqyG89EaO7FzkJ YFHnWARzlyWwCjEEkI7xATVv35abhLOMwFChgfdkPiNtT1KSLsOO9GCukMZMD9HWBmJ1 if2192BUb5eXh2Idg9ZmQYFhNm5R8OLWgvUHAL8dt5HobH0ZoRM0FgY38FEHxbu5dmDU 286Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=oeWF7hH7n+Tw7lHBL5J+ZOk4gNTM5rWwWdN9L8sozQY=; b=whvSO8Rvysm6gG16wAv5ng74UQATUxG/It5giwka1Gzc4RZPqP2yNyx5E4yNqNLKKy GIhr7SVqKRu+bqMCP8hinXlbNd8MDhpDAmJAitryiNFb2Cz10gnb7Dw912UOFAb6UZw+ UXp4Y3rINMKZoCiw2Spkrqx6KgXdBZsI3pNTP8PLUHXfe/XgEhKFK1ziZ9hSj6CrxQdQ 3hhNNjq5+q2oIwvw0Rrx8qM4e0cZFviuivIB1W+aJVTRUGnnPMN+ROeizsg/wr6Htm5+ u80ZMUQ5pn3RFHv2qc8nxoU1ZjJCvc50TzqtphPDEM+sYMy5bCneUbdp7eZMJvn8ipEU NEBw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-acpi-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=huawei.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id ds2si13913381ejc.749.2021.04.20.02.28.59; Tue, 20 Apr 2021 02:28:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-acpi-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-acpi-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=huawei.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231300AbhDTJ33 (ORCPT + 4 others); Tue, 20 Apr 2021 05:29:29 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:16607 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229494AbhDTJ33 (ORCPT ); Tue, 20 Apr 2021 05:29:29 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4FPdbv2TP3z19M25; Tue, 20 Apr 2021 17:26:35 +0800 (CST) Received: from A2006125610.china.huawei.com (10.47.83.26) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.498.0; Tue, 20 Apr 2021 17:28:45 +0800 From: Shameer Kolothum To: , , CC: , , , , , , , , , Subject: [PATCH v3 07/10] iommu/arm-smmu-v3: Get associated RMR info and install bypass STE Date: Tue, 20 Apr 2021 10:27:48 +0200 Message-ID: <20210420082751.1829-8-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20210420082751.1829-1-shameerali.kolothum.thodi@huawei.com> References: <20210420082751.1829-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.83.26] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org Check if there is any RMR info associated with the devices behind the SMMUv3 and if any, install bypass STEs for them. This is to keep any ongoing traffic associated with these devices alive when we enable/reset SMMUv3 during probe(). Signed-off-by: Shameer Kolothum --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 35 +++++++++++++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ 2 files changed, 37 insertions(+) -- 2.17.1 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 190285812182..14e9c7034c04 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3530,6 +3530,37 @@ static void __iomem *arm_smmu_ioremap(struct device *dev, resource_size_t start, return devm_ioremap_resource(dev, &res); } +static void arm_smmu_rmr_install_bypass_ste(struct arm_smmu_device *smmu) +{ + struct iommu_rmr *e; + int ret; + + /* + * Since, we don't have a mechanism to differentiate the RMR + * SIDs that has an ongoing live stream, install bypass STEs + * for all the reported ones.  + */ + list_for_each_entry(e, &smmu->rmr_list, list) { + __le64 *step; + + ret = arm_smmu_init_sid_strtab(smmu, e->sid); + if (ret) { + dev_err(smmu->dev, "RMR bypass(0x%x) failed\n", + e->sid); + continue; + } + + step = arm_smmu_get_step_for_sid(smmu, e->sid); + arm_smmu_write_strtab_ent(NULL, e->sid, step, true); + } +} + +static int arm_smmu_get_rmr(struct arm_smmu_device *smmu) +{ + INIT_LIST_HEAD(&smmu->rmr_list); + return iommu_dma_get_rmrs(dev_fwnode(smmu->dev), &smmu->rmr_list); +} + static int arm_smmu_device_probe(struct platform_device *pdev) { int irq, ret; @@ -3613,6 +3644,10 @@ static int arm_smmu_device_probe(struct platform_device *pdev) /* Record our private device structure */ platform_set_drvdata(pdev, smmu); + /* Check for RMRs and install bypass STEs if any */ + if (!arm_smmu_get_rmr(smmu)) + arm_smmu_rmr_install_bypass_ste(smmu); + /* Reset the device */ ret = arm_smmu_device_reset(smmu, bypass); if (ret) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index f985817c967a..e210fa81538a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -639,6 +639,8 @@ struct arm_smmu_device { /* IOMMU core code handle */ struct iommu_device iommu; + + struct list_head rmr_list; }; /* SMMU private data for each master */