From patchwork Tue Apr 20 08:27:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 424559 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp206778jao; Tue, 20 Apr 2021 02:28:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwCNRoOghx2HotQJJHiMg46MyxIpM6+wPqqexxwnI37z/+Aw70/gNMwFPB772a8UcLx6hGK X-Received: by 2002:a05:6402:354b:: with SMTP id f11mr30739509edd.361.1618910929135; Tue, 20 Apr 2021 02:28:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1618910929; cv=none; d=google.com; s=arc-20160816; b=XYXsKxid+EzvMoC49ctrZnZNJaptYjE0ItGidaNkspziidcLqA3p845CA/59BDuBAg +XKij6jcC34+Ww6UYScz9r/BGhBOwL2ToTYdl8us0DGS2zt2NV5OiqrtN9O8iswMKKWk 2uGU5pjbuPsJMh4EuAPf0wic1LCoVUYr5la5tfKs1EhgBTR4y5C73QqWJlsnJAYHSNz3 9AecbBnpWle6C79JiqHQE1d+D02qRu0uoovoscSAV+387ZIiP9DuU20YUvQFiiizO2VM suoJ7neNpCRuzviCXM5LBL6y2Wr/OjDuov5iJtHYfPqg9gecZky5qEJqMm0sPdwHfQHR KyAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=6pMNzma1IHzrNA80hXIWwlnMBZ5bik8aJVXmPO2xxeE=; b=NkdkeDxmm5imn7yRcRKq2Wb/Im8AnxKaf5dxpGkLE2dlBtYaPTgiwGOYJIretdKTIp o56DsKQI7tGPGl1lriefATG96Vr2wf7G49jpgT5Rj8hZQOb0KFFT3sM2/tqtArPU70A4 BvU1gFS92wvMWxoNEP9gjhW1ZXUL738AeALgcZbP2Rdh0hz0CGavmjoi8yr9nivCKhDv /sBf1V4kRFgXWfiyLfjU/NwCl1cDuD8vDW+N0tMyPoCL5aQ6+YXq2+01mpYkkT5kQH0N e4JIZFRCN1ozrE/LxRnuDlrbyXMo5h/rLTmF1wM8syx6Jpn8oQVGRKdvR9YdCnj213vM EZXQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-acpi-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=huawei.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id i2si5177143edq.3.2021.04.20.02.28.48; Tue, 20 Apr 2021 02:28:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-acpi-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-acpi-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=huawei.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229761AbhDTJ3T (ORCPT + 4 others); Tue, 20 Apr 2021 05:29:19 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:16485 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229494AbhDTJ3S (ORCPT ); Tue, 20 Apr 2021 05:29:18 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4FPdbj2CmDzrf4J; Tue, 20 Apr 2021 17:26:25 +0800 (CST) Received: from A2006125610.china.huawei.com (10.47.83.26) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.498.0; Tue, 20 Apr 2021 17:28:38 +0800 From: Shameer Kolothum To: , , CC: , , , , , , , , , Subject: [PATCH v3 06/10] =?utf-8?q?iommu/arm-smmu-v3=3A_Add_bypass_flag_t?= =?utf-8?b?b8KgYXJtX3NtbXVfd3JpdGVfc3RydGFiX2VudCgp?= Date: Tue, 20 Apr 2021 10:27:47 +0200 Message-ID: <20210420082751.1829-7-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20210420082751.1829-1-shameerali.kolothum.thodi@huawei.com> References: <20210420082751.1829-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.83.26] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org By default, disable_bypass is set and any dev without an iommu domain installs STE with CFG_ABORT during arm_smmu_init_bypass_stes(). Introduce a "bypass" flag to arm_smmu_write_strtab_ent() so that we can force it to install CFG_BYPASS STE for specific SIDs. This will be useful for RMR related SIDs. Signed-off-by: Shameer Kolothum --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 29da3b681621..190285812182 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1176,7 +1176,7 @@ static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid) } static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, - __le64 *dst) + __le64 *dst, bool bypass) { /* * This is hideously complicated, but we only really care about @@ -1247,7 +1247,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, /* Bypass/fault */ if (!smmu_domain || !(s1_cfg || s2_cfg)) { - if (!smmu_domain && disable_bypass) + if (!smmu_domain && disable_bypass && !bypass) val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT); else val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS); @@ -1322,7 +1322,7 @@ static void arm_smmu_init_bypass_stes(__le64 *strtab, unsigned int nent) unsigned int i; for (i = 0; i < nent; ++i) { - arm_smmu_write_strtab_ent(NULL, -1, strtab); + arm_smmu_write_strtab_ent(NULL, -1, strtab, false); strtab += STRTAB_STE_DWORDS; } } @@ -2076,7 +2076,7 @@ static void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master) if (j < i) continue; - arm_smmu_write_strtab_ent(master, sid, step); + arm_smmu_write_strtab_ent(master, sid, step, false); } }