From patchwork Thu Nov 19 12:11:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 328407 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:5ce:0:0:0:0 with SMTP id l14csp361548ils; Thu, 19 Nov 2020 04:13:55 -0800 (PST) X-Google-Smtp-Source: ABdhPJx+/ztJ8lLepslsWbkIb3ZMXQ0RaU25ZBM2TanBnVQ1NmIQ+5cAT+GVJIj+E1OCRtM60KR+ X-Received: by 2002:a50:e087:: with SMTP id f7mr18510493edl.29.1605788035260; Thu, 19 Nov 2020 04:13:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1605788035; cv=none; d=google.com; s=arc-20160816; b=JjI7Eldekrv9qGLGnKzpQSyeiLi5ocLnfIEtquDYfr73ANtpPLzHgzSBZqjDpg1IKQ vdUA/ixbqCXRZBWTPRPdmuumlAdQ2R/0fwIlYe41e4aIjmhcuuMrBV3anCFUKXoRL61S 7q8noOjPcC3LmbhxbyU6+no+LQX+HIRwPLOvndyLppzeUxXQidGilC+LrjU6rXkiGSSi gFeP4EGexcHUJYxR/ce3yyQvWxnHs03sNYge12oxD8R6l6VLzCMaWiqXxxSFnkJifW2x CwxXT3cEuQ89ZYQVz6KVDcuY0ueENSmREnAJrPZVmrUV+LjMB8H7yn/363Kq2KJInBQq Bv3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=fx+YdgHdGfXz3R2yYdhVUlHrZME/JEaeL0kHjwNjbvs=; b=R40Qiauzx6DIMiJD/464irLSwMBVoStDDR8sMozY6fq5l7tPCu05c1xBGe0MkkYWnm owgL+IzDq8z7UkqnxOk15qjRWB8dFofKfzocae4laJ3rqaU+SUbsbjw6aRjrz9DyfY7h KaRHegN08MBg/HOIBEIgn6E1ycaEP9ChNhvOP3zU0Nfwg0Rbkn61bY5GDmzK5yVcbChO 5vn9p1jG/w4Rav+D68r2e8X8DXi0r4LHlSykm6pE70OUb6FBHdJP5T5cpNhCQOI3QkhU 6vFfXgG3auuIbUK4QlG7N+M7oOdVeUujln5I19TCJDCnvxFIsIFSccphUPI+S5YTpVSZ vYPQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-acpi-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id qc4si16705640ejb.188.2020.11.19.04.13.55; Thu, 19 Nov 2020 04:13:55 -0800 (PST) Received-SPF: pass (google.com: domain of linux-acpi-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-acpi-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727270AbgKSMNN (ORCPT + 5 others); Thu, 19 Nov 2020 07:13:13 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:7565 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726691AbgKSMNM (ORCPT ); Thu, 19 Nov 2020 07:13:12 -0500 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4CcJV00Bwhzhd20; Thu, 19 Nov 2020 20:12:56 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.210.168.73) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.487.0; Thu, 19 Nov 2020 20:13:02 +0800 From: Shameer Kolothum To: , , , CC: , , , , , , , , Subject: [RFC PATCH v2 7/8] iommu/arm-smmu-v3: Get associated RMR info and install bypass STE Date: Thu, 19 Nov 2020 12:11:49 +0000 Message-ID: <20201119121150.3316-8-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20201119121150.3316-1-shameerali.kolothum.thodi@huawei.com> References: <20201119121150.3316-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.210.168.73] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org Check if there is any RMR info associated with the devices behind the SMMUv3 and if any, install bypass STEs for them. This is to keep any ongoing traffic associated with these devices alive when we enable/reset SMMUv3 during probe(). Signed-off-by: Shameer Kolothum --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 40 +++++++++++++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ 2 files changed, 42 insertions(+) -- 2.17.1 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 5f366d5a9ebf..97df1df001c9 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3486,6 +3486,42 @@ static void __iomem *arm_smmu_ioremap(struct device *dev, resource_size_t start, return devm_ioremap_resource(dev, &res); } +static void arm_smmu_rmr_install_bypass_ste(struct arm_smmu_device *smmu) +{ + struct iommu_rmr *e; + int i, ret; + + /* + * Since, we don't have a mechanism to differentiate the RMR + * SIDs that has an ongoing live stream, install bypass STEs + * for all the reported ones.  + * FixMe: Avoid duplicate SIDs in the list as one sid may + * associate with multiple RMRs. + */ + list_for_each_entry(e, &smmu->rmr_list, list) { + for (i = 0; i < e->num_ids; i++) { + __le64 *step; + u32 sid = e->ids[i]; + + ret = arm_smmu_init_sid_strtab(smmu, sid); + if (ret) { + dev_err(smmu->dev, "RMR bypass(0x%x) failed\n", + sid); + continue; + } + + step = arm_smmu_get_step_for_sid(smmu, sid); + arm_smmu_write_strtab_ent(NULL, sid, step, true); + } + } +} + +static int arm_smmu_get_rmr(struct arm_smmu_device *smmu) +{ + INIT_LIST_HEAD(&smmu->rmr_list); + return iommu_dma_get_rmrs(dev_fwnode(smmu->dev), &smmu->rmr_list); +} + static int arm_smmu_device_probe(struct platform_device *pdev) { int irq, ret; @@ -3569,6 +3605,10 @@ static int arm_smmu_device_probe(struct platform_device *pdev) /* Record our private device structure */ platform_set_drvdata(pdev, smmu); + /* Check for RMRs and install bypass STEs if any */ + if (!arm_smmu_get_rmr(smmu)) + arm_smmu_rmr_install_bypass_ste(smmu); + /* Reset the device */ ret = arm_smmu_device_reset(smmu, bypass); if (ret) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index d4b7f40ccb02..17b517ddecee 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -636,6 +636,8 @@ struct arm_smmu_device { /* IOMMU core code handle */ struct iommu_device iommu; + + struct list_head rmr_list; }; /* SMMU private data for each master */