| Message ID | 20200830125753.230420-14-hdegoede@redhat.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v8,01/17] ACPI / LPSS: Resume Cherry Trail PWM controller in no-irq phase | expand |
On Sun, Aug 30, 2020 at 02:57:49PM +0200, Hans de Goede wrote: > Implement the pwm_ops.get_state() method to complete the support for the > new atomic PWM API. > > Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > Signed-off-by: Hans de Goede <hdegoede@redhat.com> > --- > Changes in v6: > - Rebase on 5.9-rc1 > - Use DIV_ROUND_UP_ULL because pwm_state.period and .duty_cycle are now u64 > > Changes in v5: > - Fix an indentation issue > > Changes in v4: > - Use DIV_ROUND_UP when calculating the period and duty_cycle from the > controller's register values > > Changes in v3: > - Add Andy's Reviewed-by tag > - Remove extra whitespace to align some code after assignments (requested by > Uwe Kleine-König) > --- > drivers/pwm/pwm-crc.c | 31 +++++++++++++++++++++++++++++++ > 1 file changed, 31 insertions(+) Acked-by: Thierry Reding <thierry.reding@gmail.com>
diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c index 27dc30882424..ecfdfac0c2d9 100644 --- a/drivers/pwm/pwm-crc.c +++ b/drivers/pwm/pwm-crc.c @@ -121,8 +121,39 @@ static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, return 0; } +static void crc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct crystalcove_pwm *crc_pwm = to_crc_pwm(chip); + struct device *dev = crc_pwm->chip.dev; + unsigned int clk_div, clk_div_reg, duty_cycle_reg; + int error; + + error = regmap_read(crc_pwm->regmap, PWM0_CLK_DIV, &clk_div_reg); + if (error) { + dev_err(dev, "Error reading PWM0_CLK_DIV %d\n", error); + return; + } + + error = regmap_read(crc_pwm->regmap, PWM0_DUTY_CYCLE, &duty_cycle_reg); + if (error) { + dev_err(dev, "Error reading PWM0_DUTY_CYCLE %d\n", error); + return; + } + + clk_div = (clk_div_reg & ~PWM_OUTPUT_ENABLE) + 1; + + state->period = + DIV_ROUND_UP(clk_div * NSEC_PER_USEC * 256, PWM_BASE_CLK_MHZ); + state->duty_cycle = + DIV_ROUND_UP_ULL(duty_cycle_reg * state->period, PWM_MAX_LEVEL); + state->polarity = PWM_POLARITY_NORMAL; + state->enabled = !!(clk_div_reg & PWM_OUTPUT_ENABLE); +} + static const struct pwm_ops crc_pwm_ops = { .apply = crc_pwm_apply, + .get_state = crc_pwm_get_state, }; static int crystalcove_pwm_probe(struct platform_device *pdev)