From patchwork Fri May 3 23:24:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 163338 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp1197965ill; Fri, 3 May 2019 16:24:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqwonSlG7+pr43MnPCCh0rW6vCQD3gZnbfpAk88VbTPqJMC7ZMDj4Q5QW0kPGXeLiyj/02ws X-Received: by 2002:a17:902:20e2:: with SMTP id v31mr10324099plg.138.1556925871879; Fri, 03 May 2019 16:24:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556925871; cv=none; d=google.com; s=arc-20160816; b=yokboMq4nyRbwTHyn1qNUgM5kD0zfRfvD1/QEGHVGy1/hFGofwWu3zoG9tE5Gp/pKk EmsDNpnS39syHrSELtBeZOxtwAa60KDnzT4gjLqcvJamgzD6HyyR48bj0Pp+VJajIG4t JDBoYc0T2BtzUK7oniANOn3qpzZMDMHckguIy947XUjqM6ezQsfJaj0zgr8BjeKRXld9 CNQUswF+rnedeRgJYnMm7XBPym41L8qaw+TdXPFhohY5J79XkP2q08+kYn30ZAkH7ajw lhAcdU1RrLxj+zr0vOyHZ3A6P94+z94u+OrLblkxExWK91zev/JvbBGG6PkRaPnidDga wBNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=StTsLO6SMOUepI5f+v08l9yaL1SFV6RZQ5mCwZlNpUw=; b=ZC6fOctskagaaIturXxGUzk6mLM+4PtWkqjqJW4nQo8F1p0eU24bWKOW1SjvN8tjDn nLlIlprx1wc+Q06apee/Hn4AsVAH1jeW4tLy6GfDZCkEf99YtJgY4GEZgleBroZnuFVE TsAHOHl4QuD7YvZT8jzS0Vzc/ZoEyffnZpyrIM4R3lTxlDX+fF0PT8Zu6QV2icwQqkHJ Oupj/uSXxFQAAcVBOjh24EClP9f4Wke8lArZ9JIs8h390cF4+FyUpkdEDps2VxeEyItK YNbcgtJq0N5rlZ+JA8sono4ABcBUQ/2X0+37cvpCtlQC6WNps6f3c9B1KrBxX0zzxTcR jMEg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x3si4677027plv.33.2019.05.03.16.24.31; Fri, 03 May 2019 16:24:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726041AbfECXYb (ORCPT + 9 others); Fri, 3 May 2019 19:24:31 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:40208 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726059AbfECXY3 (ORCPT ); Fri, 3 May 2019 19:24:29 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 229771684; Fri, 3 May 2019 16:24:29 -0700 (PDT) Received: from mammon-tx2.austin.arm.com (mammon-tx2.austin.arm.com [10.118.29.246]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8D0243F557; Fri, 3 May 2019 16:24:28 -0700 (PDT) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: linux-acpi@vger.kernel.org, catalin.marinas@arm.com, will.deacon@arm.com, rjw@rjwysocki.net, lenb@kernel.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, sudeep.holla@arm.com, linuxarm@huawei.com, john.garry@huawei.com, Jeremy Linton Subject: [PATCH v3 4/5] arm_pmu: acpi: spe: Add initial MADT/SPE probing Date: Fri, 3 May 2019 18:24:06 -0500 Message-Id: <20190503232407.37195-5-jeremy.linton@arm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190503232407.37195-1-jeremy.linton@arm.com> References: <20190503232407.37195-1-jeremy.linton@arm.com> MIME-Version: 1.0 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org ACPI 6.3 adds additional fields to the MADT GICC structure to describe SPE PPI's. We pick these out of the cached reference to the madt_gicc structure similarly to the core PMU code. We then create a platform device referring to the IRQ and let the user/module loader decide whether to load the SPE driver. Signed-off-by: Jeremy Linton --- arch/arm64/include/asm/acpi.h | 3 ++ drivers/perf/Kconfig | 5 +++ drivers/perf/arm_pmu_acpi.c | 76 +++++++++++++++++++++++++++++++++++ include/linux/perf/arm_pmu.h | 2 + 4 files changed, 86 insertions(+) -- 2.21.0 diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h index 7628efbe6c12..d10399b9f998 100644 --- a/arch/arm64/include/asm/acpi.h +++ b/arch/arm64/include/asm/acpi.h @@ -41,6 +41,9 @@ (!(entry) || (entry)->header.length < ACPI_MADT_GICC_MIN_LENGTH || \ (unsigned long)(entry) + (entry)->header.length > (end)) +#define ACPI_MADT_GICC_SPE (ACPI_OFFSET(struct acpi_madt_generic_interrupt, \ + spe_interrupt) + sizeof(u16)) + /* Basic configuration for ACPI */ #ifdef CONFIG_ACPI pgprot_t __acpi_get_mem_attribute(phys_addr_t addr); diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index af9bc178495d..bc2647c64c9d 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -52,6 +52,11 @@ config ARM_PMU_ACPI depends on ARM_PMU && ACPI def_bool y +config ARM_SPE_ACPI + depends on ARM_PMU_ACPI && ARM_SPE_PMU + def_bool y + + config ARM_DSU_PMU tristate "ARM DynamIQ Shared Unit (DSU) PMU" depends on ARM64 diff --git a/drivers/perf/arm_pmu_acpi.c b/drivers/perf/arm_pmu_acpi.c index 0f197516d708..b0244e1e8c91 100644 --- a/drivers/perf/arm_pmu_acpi.c +++ b/drivers/perf/arm_pmu_acpi.c @@ -74,6 +74,80 @@ static void arm_pmu_acpi_unregister_irq(int cpu) acpi_unregister_gsi(gsi); } +#ifdef CONFIG_ARM_SPE_ACPI +static struct resource spe_resources[] = { + { + /* irq */ + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device spe_dev = { + .name = ARMV8_SPE_PDEV_NAME, + .id = -1, + .resource = spe_resources, + .num_resources = ARRAY_SIZE(spe_resources) +}; + +/* + * For lack of a better place, hook the normal PMU MADT walk + * and create a SPE device if we detect a recent MADT with + * a homogeneous PPI mapping. + */ +static int arm_spe_acpi_register_device(void) +{ + int cpu, ret, irq; + int hetid; + u16 gsi = 0; + bool first = true; + + struct acpi_madt_generic_interrupt *gicc; + + /* + * sanity check all the GICC tables for the same interrupt number + * for now we only support homogeneous ACPI/SPE machines. + */ + for_each_possible_cpu(cpu) { + gicc = acpi_cpu_get_madt_gicc(cpu); + + if (gicc->header.length < ACPI_MADT_GICC_SPE) + return -ENODEV; + if (first) { + gsi = gicc->spe_interrupt; + if (!gsi) + return -ENODEV; + hetid = find_acpi_cpu_topology_hetero_id(cpu); + first = false; + } else if ((gsi != gicc->spe_interrupt) || + (hetid != find_acpi_cpu_topology_hetero_id(cpu))) { + pr_warn("ACPI: SPE must be homogeneous\n"); + return -EINVAL; + } + } + + irq = acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, + ACPI_ACTIVE_HIGH); + if (irq < 0) { + pr_warn("ACPI: SPE Unable to register interrupt: %d\n", gsi); + return irq; + } + + spe_resources[0].start = irq; + ret = platform_device_register(&spe_dev); + if (ret < 0) { + pr_warn("ACPI: SPE: Unable to register device\n"); + acpi_unregister_gsi(gsi); + } + + return ret; +} +#else +static inline int arm_spe_acpi_register_device(void) +{ + return -ENODEV; +} +#endif /* CONFIG_ARM_SPE_ACPI */ + static int arm_pmu_acpi_parse_irqs(void) { int irq, cpu, irq_cpu, err; @@ -279,6 +353,8 @@ static int arm_pmu_acpi_init(void) if (acpi_disabled) return 0; + arm_spe_acpi_register_device(); /* failures are expected */ + ret = arm_pmu_acpi_parse_irqs(); if (ret) return ret; diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index 4641e850b204..784bc58f165a 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -175,4 +175,6 @@ void armpmu_free_irq(int irq, int cpu); #endif /* CONFIG_ARM_PMU */ +#define ARMV8_SPE_PDEV_NAME "arm,spe-v1" + #endif /* __ARM_PMU_H__ */