From patchwork Wed Dec 13 11:58:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 121734 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp5373736qgn; Wed, 13 Dec 2017 04:01:06 -0800 (PST) X-Google-Smtp-Source: ACJfBotaSu+9VAW1+ppfbB6pzMKTmd1hbCWgKQLTFF+YWtJjrxx2Vy3YT10JoXQbvaSZMlRyOKHm X-Received: by 10.84.235.2 with SMTP id o2mr5628942plk.64.1513166465925; Wed, 13 Dec 2017 04:01:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513166465; cv=none; d=google.com; s=arc-20160816; b=hhrAXjsj0Hs2gBUDnmXUq/e1zNdpNA44550IArEJ+DgM+AQ9JiymhAgNe6u1JcQCVa txP5lGxuIiI4rGlXrAsfs7OXzJZwiIKB9RwB6L4zCFfnOw04hTC9+sKCILnFa4lTVrhW dR0Rcj4PfRYjkVqUyAObD2Yp+JExw8mW+4BQRkOTdeBX2iAMJFR0LhAQj5P5wrVmulCP 2nyUzf3kvr5oftmrCCtXFsaCAGeF+cpXI5BdV586VXkNTL+GKNe+7QfwUStvsYjoc/jN +Q1rg9W3AYlJq3BSUioVTYr8fpWqooL72/lsHZiNY/A0IVLhfBVIysVqaQkSnjVG5iul Cqxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=o19kW1wLU8MDIujGimkwGPqEQv4H208yUdU1wSK/zyc=; b=xVLmgfFgrqjqQyyDYJuU/8CR/RcentPP+E73QA9IzolKN1u4pUN9qqluDFXKSwgjMb Xs4bizvl+oAChRrl02t71Vb8jiLrk/dlUuQBbNYVdDw3JszYtaQlvRQ9hQKYqRjD2uIl zMvZZG3ru+JO1hld2kzJxdrm8G80R5ecMPdoxtz8lmA3JU1kYceynJJRjQtBAVCRrSRK TB2RnggZAHilMYdftTXRULuy0GVLiCjuIESCZNFcPacE/56ut57ya85Nnc838NySibGY h+p4yLo3665b1V1CC4E4/973Hq8kCM6TfSQoTrP0AF+YtXHgZjQ8mjkqJWYxbzt+DCPl dT5g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t8si1285240pfh.310.2017.12.13.04.01.05; Wed, 13 Dec 2017 04:01:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752623AbdLMMBE (ORCPT + 7 others); Wed, 13 Dec 2017 07:01:04 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:2283 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752603AbdLMMBE (ORCPT ); Wed, 13 Dec 2017 07:01:04 -0500 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 70049B80BB334; Wed, 13 Dec 2017 20:00:47 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.361.1; Wed, 13 Dec 2017 20:00:39 +0800 From: Shameer Kolothum To: , , , CC: , , , , , , , , , Shameer Kolothum Subject: [PATCH v11 3/3] arm64:dts:hisilicon Disable hisilicon smmu node on hip06/hip07 Date: Wed, 13 Dec 2017 11:58:30 +0000 Message-ID: <20171213115830.61872-4-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20171213115830.61872-1-shameerali.kolothum.thodi@huawei.com> References: <20171213115830.61872-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms hip06/hip07 to support the SMMUv3 mappings for MSI transactions. PCIe controller on these platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This makes it difficult for these platforms to have SMMU translation for MSI. In order to workaround this, ARM SMMUv3 driver requires a quirk to treat the MSI regions separately. Such a quirk is currently missing for DT based systems and therefore we need to explicitly disable the hip06/hip07 smmu entries in dts. Signed-off-by: Shameer Kolothum Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 55 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/hisilicon/hip07.dtsi | 24 ++++++++++++++ 2 files changed, 79 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index a049b64..d0d5933 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -291,6 +291,13 @@ #interrupt-cells = <2>; num-pins = <128>; }; + + mbigen_pcie0: intc_pcie0 { + msi-parent = <&its_dsa 0x40085>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <10>; + }; }; mbigen_dsa@c0080000 { @@ -312,6 +319,30 @@ }; }; + /** HiSilicon erratum 161010801: This describes the limitation + * of HiSilicon platforms hip06/hip07 to support the SMMUv3 + * mappings for PCIe MSI transactions. + * PCIe controller on these platforms has to differentiate the + * MSI payload against other DMA payload and has to modify the + * MSI payload. This makes it difficult for these platforms to + * have a SMMU translation for MSI. In order to workaround this, + * ARM SMMUv3 driver requires a quirk to treat the MSI regions + * separately. Such a quirk is currently missing for DT based + * systems. Hence please make sure that the smmu pcie node on + * hip06 is disabled as this will break the PCIe functionality + * when iommu-map entry is used along with the PCIe node. + * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html + */ + smmu0: smmu_pcie { + compatible = "arm,smmu-v3"; + reg = <0x0 0xa0040000 0x0 0x20000>; + #iommu-cells = <1>; + dma-coherent; + smmu-cb-memtype = <0x0 0x1>; + hisilicon,broken-prefetch-cmd; + status = "disabled"; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -676,6 +707,30 @@ <637 1>,<638 1>,<639 1>; status = "disabled"; }; + + pcie0: pcie@a0090000 { + compatible = "hisilicon,hip06-pcie-ecam"; + reg = <0 0xb0000000 0 0x2000000>, + <0 0xa0090000 0 0x10000>; + bus-range = <0 31>; + msi-map = <0x0000 &its_dsa 0x0000 0x2000>; + msi-map-mask = <0xffff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 + 0x5ff0000 0x01000000 0 0 0 0xb7ff0000 + 0 0x10000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4 + 0x0 0 0 2 &mbigen_pcie0 650 4 + 0x0 0 0 3 &mbigen_pcie0 650 4 + 0x0 0 0 4 &mbigen_pcie0 650 4>; + status = "disabled"; + }; + }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 2c01a21..58fe013 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1083,6 +1083,30 @@ }; }; + /** HiSilicon erratum 161010801: This describes the limitation + * of HiSilicon platforms hip06/hip07 to support the SMMUv3 + * mappings for PCIe MSI transactions. + * PCIe controller on these platforms has to differentiate the + * MSI payload against other DMA payload and has to modify the + * MSI payload. This makes it difficult for these platforms to + * have a SMMU translation for MSI. In order to workaround this, + * ARM SMMUv3 driver requires a quirk to treat the MSI regions + * separately. Such a quirk is currently missing for DT based + * systems. Hence please make sure that the smmu pcie node on + * hip06 is disabled as this will break the PCIe functionality + * when iommu-map entry is used along with the PCIe node. + * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html + */ + smmu0: smmu_pcie { + compatible = "arm,smmu-v3"; + reg = <0x0 0xa0040000 0x0 0x20000>; + #iommu-cells = <1>; + dma-coherent; + smmu-cb-memtype = <0x0 0x1>; + hisilicon,broken-prefetch-cmd; + status = "disabled"; + }; + soc { compatible = "simple-bus"; #address-cells = <2>;