From patchwork Fri Oct 6 14:04:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 115070 Delivered-To: patch@linaro.org Received: by 10.80.163.170 with SMTP id s39csp1411144edb; Fri, 6 Oct 2017 07:08:08 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDlPzjMwxpvHYgDyg+u/n0XScahImQcHLN5/07U2Ud9obfkQy8nGIvuCfyJMvBNA5yTt8L+ X-Received: by 10.98.56.18 with SMTP id f18mr2294866pfa.81.1507298888488; Fri, 06 Oct 2017 07:08:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507298888; cv=none; d=google.com; s=arc-20160816; b=YhiYEOwlKTe2YriRsG2CYpZFrePi/sSpk2qMKdlQDdnLBDo05Dg5AX2SYds1Nq1G5N xFt+Et7jsxsP9gDmAEi5e5ipP7OS8q3EG4FfgA2vgxXgiMzqnVVJMItts0bU4pGQ5a+I wktwyePvY1CT4iwXl+A2NMuvKKilOHOhAT2BF+Mvf8nggDUMIdhtizfJ01J/aNowtTVs 2FGGRHUs1r9MwFmEHcKfG66UvOhdYwSIxu+kIuZ1WzWHomQoPdnzPpow6+cQ4Mj3bSH/ UEIHRC01gyqQInu3rV/k5Cy7P1ptk70NmII1hxRYifLDxKyHOIHK26WUNgBA9y42lDIw S/qQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=L2YA/6fLjE9aOcIvNhmR3UKQbSzCT7Pu+RC6x7cQ2fY=; b=Y5WsonmqOYRR284N+wVWBaxklcAiLvDdFn8nZ/NbrhAFihwLK4v/4ja18vLgdrkeCV a5I5Ae5Vt540VPwG/pcaBozYfHyoBtnwuk98JVTSyVFiWDOfRYDP7HERTTXuxnl4L7iA yLViVpPQwM9wv0R68sufTltvq/VJ7Frt2nm9D3guuhLLSsXTIcFj/HRwMWQQNHUY3C6t iiK9v5Lihau5uP4PV3pVKZpvLojg/EvS8MSYQZcsAVok//vyYC+i0KkwI2JCYgXUK8mV Seef/DW5AQpKtb+Q0JjHPHu6zpQuenryniMxdfkjH0PZ+15DnwSelgKwiax2Li+DbLGw wVow== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j8si1229982plk.805.2017.10.06.07.08.07; Fri, 06 Oct 2017 07:08:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751654AbdJFOIG (ORCPT + 7 others); Fri, 6 Oct 2017 10:08:06 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:7499 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751757AbdJFOIA (ORCPT ); Fri, 6 Oct 2017 10:08:00 -0400 Received: from 172.30.72.58 (EHLO DGGEMS403-HUB.china.huawei.com) ([172.30.72.58]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DIO33389; Fri, 06 Oct 2017 22:07:53 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.301.0; Fri, 6 Oct 2017 22:07:31 +0800 From: Shameer Kolothum To: , , , , , , , CC: , , , , , , , , , Shameer Kolothum Subject: [PATCH v9 3/4] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 Date: Fri, 6 Oct 2017 15:04:49 +0100 Message-ID: <20171006140450.89652-4-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20171006140450.89652-1-shameerali.kolothum.thodi@huawei.com> References: <20171006140450.89652-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.59D78E3A.0087, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: e0bac6cc5fe5acfa64a483feaa321cba Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms Hip06/Hip07 to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements a ACPI table based quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. Signed-off-by: Shameer Kolothum --- drivers/iommu/arm-smmu-v3.c | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index e67ba6c..dd42ae9 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -608,6 +608,7 @@ struct arm_smmu_device { #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) #define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) +#define ARM_SMMU_OPT_RESV_HW_MSI (1 << 2) u32 options; struct arm_smmu_cmdq cmdq; @@ -1934,14 +1935,29 @@ static void arm_smmu_get_resv_regions(struct device *dev, struct list_head *head) { struct iommu_resv_region *region; + struct arm_smmu_master_data *master = dev->iommu_fwspec->iommu_priv; + struct arm_smmu_device *smmu = master->smmu; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + int resv = 0; - region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI); - if (!region) - return; + if ((smmu->options & ARM_SMMU_OPT_RESV_HW_MSI)) { - list_add_tail(®ion->list, head); + resv = iommu_dma_get_msi_resv_regions(dev, head); + + if (resv < 0) { + dev_warn(dev, "HW MSI region resv failed: %d\n", resv); + return; + } + } + + if (!resv) { + region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, + prot, IOMMU_RESV_SW_MSI); + if (!region) + return; + + list_add_tail(®ion->list, head); + } iommu_dma_get_resv_regions(dev, head); } @@ -2667,6 +2683,7 @@ static void acpi_smmu_get_options(u32 model, struct arm_smmu_device *smmu) break; case ACPI_IORT_SMMU_HISILICON_HI161X: smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; + smmu->options |= ARM_SMMU_OPT_RESV_HW_MSI; break; }