From patchwork Wed Aug 9 10:07:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 109701 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp646847qge; Wed, 9 Aug 2017 03:09:16 -0700 (PDT) X-Received: by 10.99.165.3 with SMTP id n3mr6945064pgf.233.1502273356178; Wed, 09 Aug 2017 03:09:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502273356; cv=none; d=google.com; s=arc-20160816; b=xK8p2mUz6B2GudL1qT3Nu/V/KLJeqCwA1W5PZKXmBEFh4cRgo7ONgQDB0XvUIeRAbo fbUyFroyp75el16dQyQhquOJYbgYC3snqFaUxf915b7HW7Ra8GdLDqdAUUG3UZJ4yBKV D7PEvwPAC+c3Q1LdqZhlp6cJfDjdhp7MXyU1f5iyygNQCrsQMGVoX63wc5zry4geqr4j LywQO2xVIMVb0ER74gZQYILOwIcRhkqUNT/jPG9dBmD5bZTuDXFo5MNsf84RStLsVdo0 hb/O07nVQqVB8MWw3H0Xl/8+nj9hOhxbH41JdZJZ4N3BfbtlNbHXrhK8JI8RhCWHABUP 1WFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=+6jvpVBqPsooqVKvLfUaAQtSizz94AlGOW0IBnxLRoM=; b=wmxJ6xXfaqPKYuh4XyCDhAqxbVEgHquyn3G7gLIFD8XFUgSkWQ0Kvj+chzJG1j0OKD ODUcOZL+8/d83A8Wx/4lHUOQcHFYP/5auHr/YjN9oHJ0T+nR90fUQjKJcT8O10qnAaZ3 1yPPmj7Cm/Lyw16+JQK1/P3xr1ILdABNFamtbw2W6J3Nqj/QoQgndOyB5Ez14M0I+IXM Fc31BNIzAskg02Jzb6VUOHHCS2q8y9tenY06T/b9jEEKSXJAmI00xKE7Y/VNc2t1H7qa iGgsIFG5Ae4r6icZssTxdox9kgqS0VfsCLAPhe01TwEZkEvyRGmK+zGaI00Un+eF2fAA VS8w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l25si2513050pli.878.2017.08.09.03.09.16; Wed, 09 Aug 2017 03:09:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753059AbdHIKI5 (ORCPT + 7 others); Wed, 9 Aug 2017 06:08:57 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2599 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752991AbdHIKI4 (ORCPT ); Wed, 9 Aug 2017 06:08:56 -0400 Received: from 172.30.72.59 (EHLO DGGEMS414-HUB.china.huawei.com) ([172.30.72.59]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DEW41340; Wed, 09 Aug 2017 18:08:54 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.301.0; Wed, 9 Aug 2017 18:08:42 +0800 From: Shameer Kolothum To: , , , , , CC: , , , , , , , , , Shameer Kolothum Subject: [PATCH v6 3/3] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 Date: Wed, 9 Aug 2017 11:07:15 +0100 Message-ID: <20170809100715.870516-4-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170809100715.870516-1-shameerali.kolothum.thodi@huawei.com> References: <20170809100715.870516-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.598ADF36.0188, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 470a28ce7285a20a312d68bf87d2484c Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms Hip06/Hip07 to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements a ACPI table based quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. Signed-off-by: Shameer Kolothum --- drivers/iommu/arm-smmu-v3.c | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 568c400..6f21dd7 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -608,6 +608,7 @@ struct arm_smmu_device { #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) #define ARM_SMMU_OPT_PAGE0_REGS_ONLY (1 << 1) +#define ARM_SMMU_OPT_RESV_HW_MSI (1 << 2) u32 options; struct arm_smmu_cmdq cmdq; @@ -1934,14 +1935,29 @@ static void arm_smmu_get_resv_regions(struct device *dev, struct list_head *head) { struct iommu_resv_region *region; + struct arm_smmu_master_data *master = dev->iommu_fwspec->iommu_priv; + struct arm_smmu_device *smmu = master->smmu; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + int resv = 0; - region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI); - if (!region) - return; + if ((smmu->options & ARM_SMMU_OPT_RESV_HW_MSI)) { - list_add_tail(®ion->list, head); + resv = iommu_dma_get_msi_resv_regions(dev, head); + + if (resv < 0) { + dev_warn(dev, "HW MSI region resv failed: %d\n", resv); + return; + } + } + + if (!resv) { + region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, + prot, IOMMU_RESV_SW_MSI); + if (!region) + return; + + list_add_tail(®ion->list, head); + } iommu_dma_get_resv_regions(dev, head); } @@ -2667,6 +2683,7 @@ static void acpi_smmu_get_options(u32 model, struct arm_smmu_device *smmu) break; case ACPI_IORT_SMMU_HISILICON_HI161X: smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; + smmu->options |= ARM_SMMU_OPT_RESV_HW_MSI; break; }