From patchwork Tue Jun 13 11:48:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 105153 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp362133qgd; Tue, 13 Jun 2017 04:50:09 -0700 (PDT) X-Received: by 10.101.89.2 with SMTP id f2mr41837701pgu.237.1497354609139; Tue, 13 Jun 2017 04:50:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497354609; cv=none; d=google.com; s=arc-20160816; b=k43ES+KJlgEA+wLNWiKHkgfYMdfATZxeg7r09B5JPdg5zjDlg/a/0xA6Cbudz/h6qV dFU4ahF0J1ekpxPr68r5Jjq6+qMRmsL9M+epl5cOiqPsWuriGjJn3BZJd1+pUstUutii P3/TBMEFvGN0XsfeFz55waR2YTvQhm9i6i5hQWEl1P43bZqpxQezo19FEMgcb3mvp/Ou qmljrcubWAz9FBXHZRQFuHJrCfcx0tcsYLE5opCaY9xDAefQWlyvlhDOR0qi9UbW/8UK 778Wuejqr5quMvoYN4LnBhLBkKfSmahycfvX0+LjDmHgxhaPyRcrNRwa9jFD47QHjUvU WkrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=emdck5TW+6hJqhDlzzcoPhli+Pb2yGs/ef9Zp2SsHnI=; b=siBjpyce+hrkfjRfnY8uwTc2zfOoVmrrcdjt9VmUdD7gggvKq6A0CIyoBRPeHkNmg1 yEgrb963vboi5hfRj2JJuINZcqFOTvW3PYKjItZ88MSk/JNzJ2/4RCEUtEMu9FvsUe5c GsSouKiPTmym0p3xteM4rsfNxSTGteblDXn768l0ixFU5LuTCx0xMj43V+YQ+HT4SJUU Shldwm1z1rjfJ6mhRqz3WjmYAq3LU+8MiE2Qm16ktrkxDk77v8Z6Lb26JwusKL8YzgFa vMhpeWbLNzyfprUkraXg32bKfmBRQtNGnm4kUVTZV2BendkGirrWgnKX40Ov9gshIHPm vQbg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z73si9570643plh.548.2017.06.13.04.50.08; Tue, 13 Jun 2017 04:50:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752187AbdFMLuF (ORCPT + 8 others); Tue, 13 Jun 2017 07:50:05 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:8273 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753128AbdFMLuE (ORCPT ); Tue, 13 Jun 2017 07:50:04 -0400 Received: from 172.30.72.55 (EHLO DGGEML403-HUB.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AQF82972; Tue, 13 Jun 2017 19:50:01 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by DGGEML403-HUB.china.huawei.com (10.3.17.33) with Microsoft SMTP Server id 14.3.301.0; Tue, 13 Jun 2017 19:49:53 +0800 From: shameer To: , , , , , CC: , , , , , , , , , shameer Subject: [PATCH 2/2] iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 Date: Tue, 13 Jun 2017 12:48:29 +0100 Message-ID: <20170613114829.188036-3-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170613114829.188036-1-shameerali.kolothum.thodi@huawei.com> References: <20170613114829.188036-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020203.593FD16A.007A, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 36b61414f7b40c6cfa71bbee3e687ddd Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms Hip06/Hip07 to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements a ACPI table based quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. Signed-off-by: shameer --- drivers/iommu/arm-smmu-v3.c | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index abe4b88..2636c85 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -597,6 +597,7 @@ struct arm_smmu_device { u32 features; #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) +#define ARM_SMMU_OPT_RESV_HW_MSI (1 << 1) u32 options; struct arm_smmu_cmdq cmdq; @@ -1904,14 +1905,29 @@ static void arm_smmu_get_resv_regions(struct device *dev, struct list_head *head) { struct iommu_resv_region *region; + struct arm_smmu_device *smmu; + struct iommu_fwspec *fwspec = dev->iommu_fwspec; int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; - region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI); - if (!region) - return; + smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); - list_add_tail(®ion->list, head); + if (smmu && (smmu->options & ARM_SMMU_OPT_RESV_HW_MSI) && + dev_is_pci(dev)) { + int ret; + + ret = iort_iommu_its_get_resv_regions(dev, head); + if (ret) { + dev_warn(dev, "HW MSI region reserve failed\n"); + return; + } + } else { + region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, + prot, IOMMU_RESV_SW_MSI); + if (!region) + return; + + list_add_tail(®ion->list, head); + } iommu_dma_get_resv_regions(dev, head); } @@ -2611,6 +2627,7 @@ static void parse_driver_acpi_options(struct acpi_iort_smmu_v3 *iort_smmu, switch (iort_smmu->model) { case ACPI_IORT_SMMU_HISILICON_HI161X: smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; + smmu->options |= ARM_SMMU_OPT_RESV_HW_MSI; break; default: break;