From patchwork Wed May 17 09:12:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 99923 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp138445qge; Wed, 17 May 2017 02:14:04 -0700 (PDT) X-Received: by 10.98.70.17 with SMTP id t17mr2627283pfa.229.1495012444458; Wed, 17 May 2017 02:14:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495012444; cv=none; d=google.com; s=arc-20160816; b=oTU55WrEBc3bcZVsMS2ymeAS9+DTBKWe0HuPNGFICpmoSuzWf6fNiTNevORqsSRdf2 wZByvUezem+H7wH50m6/VnEHqg6814B3LNCmvrk4sjuyQwAJN/2+NreqlqrsSfAe7b1z k4iEXSTq/NMX4JQ9V5qFgDafTSguE7uPpikWDQSmMH5/qopv1sUGzNovo4QBWsGzRO0O wDF/8omulgohJjswvqd+Ea2dlGJyChRiBsry+8BNxsyAFSKv4WtxiEa3VyMFcHZtlnJ2 KY+jFfD76hmrZJIJXBVhj1RIStjPhaDLGszvODDuWc24e3D/4gHLA4U5tSE7v8JoLRVZ x17g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=dIUpiHYuoiBOqeAjH3XM2kEVjVTzo9iWcc3gfioASG4=; b=ZTgcIZasUDJNbYBk6SH2Y+wOWL9xghhvR4hq337DqV54KozkjsZvTYlw8u4JWGMd1q wWHVFd9Shm28NOfvexv6x5nsKYRdQo6dFXl00rWfgUUCw6Lu13R3psnlIyitgJaozH11 AdrMAKZsuwAdUb5ElFBb7HqA5oU7DQ4a2RSiabhyGl60K8+p54YdwUAMAvNJCleXFpvb rNLdWEds3TtDYcjJ6c4ClPhVGy5f5dXbqSaq9K8+izfFk1r5SD6qPZjvWKn+xhPMCzyl QSKzYvt/60u7O7uG+NaQ3xPrNZwQwQzUTaf3i9rZGtReuGhbjAlko/hsGYYdhuhz4UMu DjyQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k65si1623405pgc.142.2017.05.17.02.14.04; Wed, 17 May 2017 02:14:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754364AbdEQJOD (ORCPT + 8 others); Wed, 17 May 2017 05:14:03 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:6326 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754032AbdEQJOB (ORCPT ); Wed, 17 May 2017 05:14:01 -0400 Received: from 172.30.72.56 (EHLO DGGEML404-HUB.china.huawei.com) ([172.30.72.56]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id ANT01660; Wed, 17 May 2017 17:13:54 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by DGGEML404-HUB.china.huawei.com (10.3.17.39) with Microsoft SMTP Server id 14.3.301.0; Wed, 17 May 2017 17:13:42 +0800 From: shameer To: , , , CC: , , , , , , , , , shameer Subject: [PATCH] iommu/arm-smmu-v3: Enable ACPI based HiSilicon CMD_PREFETCH quirk(erratum 161010701) Date: Wed, 17 May 2017 10:12:05 +0100 Message-ID: <20170517091205.7752-1-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.591C1455.00AB, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: c215ceaa17b7fcf036b5c251f387496e Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org HiSilicon SMMUv3 on Hip06/Hip07 platforms doesn't support CMD_PREFETCH command. The dt based support for this quirk is already present in the driver(hisilicon,broken-prefetch-cmd). This adds ACPI support for the quirk using the IORT smmu model number. Signed-off-by: shameer Signed-off-by: hanjun --- Documentation/arm64/silicon-errata.txt | 1 + drivers/iommu/arm-smmu-v3.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 10f2ddd..d5d23d0 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -66,6 +66,7 @@ stable kernels. | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | | | | | | | Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 | +| Hisilicon | Hip0{6,7} | #161010701 | N/A | | | | | | | Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | | Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 | diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 380969a..abe4b88 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -2605,6 +2605,20 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) } #ifdef CONFIG_ACPI +static void parse_driver_acpi_options(struct acpi_iort_smmu_v3 *iort_smmu, + struct arm_smmu_device *smmu) +{ + switch (iort_smmu->model) { + case ACPI_IORT_SMMU_HISILICON_HI161X: + smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; + break; + default: + break; + } + + dev_notice(smmu->dev, "options set 0x%x\n", smmu->options); +} + static int arm_smmu_device_acpi_probe(struct platform_device *pdev, struct arm_smmu_device *smmu) { @@ -2617,6 +2631,8 @@ static int arm_smmu_device_acpi_probe(struct platform_device *pdev, /* Retrieve SMMUv3 specific data */ iort_smmu = (struct acpi_iort_smmu_v3 *)node->node_data; + parse_driver_acpi_options(iort_smmu, smmu); + if (iort_smmu->flags & ACPI_IORT_SMMU_V3_COHACC_OVERRIDE) smmu->features |= ARM_SMMU_FEAT_COHERENCY;