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[209.132.180.67]) by mx.google.com with ESMTP id c26si5622017pfl.163.2017.05.13.02.53.49; Sat, 13 May 2017 02:53:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752718AbdEMJxs (ORCPT + 8 others); Sat, 13 May 2017 05:53:48 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:6287 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751885AbdEMJxr (ORCPT ); Sat, 13 May 2017 05:53:47 -0400 Received: from 172.30.72.55 (EHLO DGGEML404-HUB.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOL14086; Sat, 13 May 2017 17:53:04 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.47.91.84) by DGGEML404-HUB.china.huawei.com (10.3.17.39) with Microsoft SMTP Server id 14.3.301.0; Sat, 13 May 2017 17:51:17 +0800 From: shameer To: , , , , CC: , , , , , , , , , , shameer Subject: [RFC v1 6/7] iommu/arm-smmu-v3: Rearrange msi resv alloc functions Date: Sat, 13 May 2017 10:47:30 +0100 Message-ID: <20170513094731.3676-7-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20170513094731.3676-1-shameerali.kolothum.thodi@huawei.com> References: <20170513094731.3676-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.47.91.84] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.5916D782.00E5, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: b1ecc8ad0eb9e58693c849ebc2e7782d Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org This moves the SW MSI reserve region allocation to probe fn. Signed-off-by: shameer --- drivers/iommu/arm-smmu-v3.c | 36 +++++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) -- 2.5.0 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index 770cc9e..e7a8a50 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -619,6 +619,9 @@ struct arm_smmu_device { /* IOMMU core code handle */ struct iommu_device iommu; + + /* MSI Reserve region */ + struct iommu_resv_region *msi_region; }; /* SMMU private data for each master */ @@ -1960,15 +1963,12 @@ static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args) static void arm_smmu_get_resv_regions(struct device *dev, struct list_head *head) { - struct iommu_resv_region *region; - int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; - - region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, - prot, IOMMU_RESV_SW_MSI); - if (!region) - return; + struct iommu_domain *domain = iommu_get_domain_for_dev(dev); + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct arm_smmu_device *smmu = smmu_domain->smmu; - list_add_tail(®ion->list, head); + if (smmu && smmu->msi_region) + list_add_tail(&smmu->msi_region->list, head); iommu_dma_get_resv_regions(dev, head); } @@ -1978,8 +1978,13 @@ static void arm_smmu_put_resv_regions(struct device *dev, { struct iommu_resv_region *entry, *next; - list_for_each_entry_safe(entry, next, head, list) + list_for_each_entry_safe(entry, next, head, list) { + if (entry->type == IOMMU_RESV_SW_MSI || + entry->type == IOMMU_RESV_MSI) + continue; + kfree(entry); + } } static struct iommu_ops arm_smmu_ops = { @@ -2711,6 +2716,17 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev, return ret; } +static struct iommu_resv_region *arm_smmu_alloc_msi_region( + struct arm_smmu_device *smmu) +{ + struct iommu_resv_region *region; + int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + + region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, + prot, IOMMU_RESV_SW_MSI); + return region; +} + static int arm_smmu_device_probe(struct platform_device *pdev) { int irq, ret; @@ -2756,6 +2772,8 @@ static int arm_smmu_device_probe(struct platform_device *pdev) if (irq > 0) smmu->gerr_irq = irq; + smmu->msi_region = arm_smmu_alloc_msi_region(smmu); + if (dev->of_node) { ret = arm_smmu_device_dt_probe(pdev, smmu); } else {