@@ -120,6 +120,7 @@ struct dsmas_entry {
struct range dpa_range;
u8 handle;
struct node_hmem_attrs hmem_attrs;
+ u16 qtg_id;
};
/* Sub-table 0: Device Scoped Memory Affinity Structure (DSMAS) */
@@ -67,6 +67,63 @@ static void dsmas_list_destroy(struct list_head *dsmas_list)
}
}
+static int cxl_port_qos_calculate(struct cxl_port *port,
+ struct list_head *dsmas_list)
+{
+ u64 sw_wr_bw, sw_wr_lat, sw_rd_bw, sw_rd_lat;
+ u64 min_rd_bw, total_rd_lat, min_wr_bw, total_wr_lat;
+ struct qtg_dsm_output *output;
+ struct qtg_dsm_input input;
+ struct dsmas_entry *dent;
+ acpi_handle handle;
+ u64 gp_bw, gp_lat;
+ u64 ds_bw, ds_lat;
+ int rc;
+
+ rc = cxl_port_get_downstream_qos(port, &ds_bw, &ds_lat);
+ if (rc)
+ return rc;
+
+ rc = cxl_port_get_switch_qos(port, &sw_rd_bw, &sw_rd_lat,
+ &sw_wr_bw, &sw_wr_lat);
+ if (rc && rc != -ENOENT)
+ return rc;
+
+ rc = cxl_acpi_get_hb_qos(port->host_bridge, &gp_lat, &gp_bw);
+ if (rc)
+ return rc;
+
+ min_rd_bw = min_t(u64, ds_bw, sw_rd_bw);
+ min_rd_bw = min_t(u64, gp_bw, min_rd_bw);
+ total_rd_lat = ds_lat + gp_lat + sw_rd_lat;
+
+ min_wr_bw = min_t(u64, ds_bw, sw_wr_bw);
+ min_wr_bw = min_t(u64, gp_bw, min_wr_bw);
+ total_wr_lat = ds_lat + gp_lat + sw_wr_lat;
+
+ handle = cxl_acpi_get_rootdev_handle(&port->dev);
+ if (IS_ERR(handle))
+ return PTR_ERR(handle);
+
+ list_for_each_entry(dent, dsmas_list, list) {
+ input.rd_lat = dent->hmem_attrs.read_latency + total_rd_lat;
+ input.wr_lat = dent->hmem_attrs.write_latency + total_wr_lat;
+ input.rd_bw = min_t(int, min_rd_bw,
+ dent->hmem_attrs.read_bandwidth);
+ input.wr_bw = min_t(int, min_wr_bw,
+ dent->hmem_attrs.write_bandwidth);
+
+ output = cxl_acpi_evaluate_qtg_dsm(handle, &input);
+ if (IS_ERR(output))
+ continue;
+
+ dent->qtg_id = output->qtg_ids[0];
+ kfree(output);
+ }
+
+ return 0;
+}
+
static int cxl_switch_port_probe(struct cxl_port *port)
{
struct cxl_hdm *cxlhdm;
@@ -165,6 +222,10 @@ static int cxl_endpoint_port_probe(struct cxl_port *port)
dev_warn(&port->dev, "Failed to parse DSMAS: %d\n", rc);
}
+ rc = cxl_port_qos_calculate(port, &dsmas_list);
+ if (rc)
+ dev_dbg(&port->dev, "Failed to do QoS calculations\n");
+
dsmas_list_destroy(&dsmas_list);
}
CXL Memory Device SW Guide rev1.0 2.11.2 provides instruction on how to caluclate latency and bandwidth for CXL memory device. Calculate minimum bandwidth and total latency for the path from the CXL device to the root port. The retrieved QTG ID is stored to the cxl_port of the CXL device. For example for a device that is directly attached to a host bus: Total Latency = Device Latency (from CDAT) + Dev to Host Bus (HB) Link Latency + Generic Port Latency Min Bandwidth = Min bandwidth for link bandwidth between HB and CXL device, device CDAT bandwidth, and Generic Port Bandwidth For a device that has a switch in between host bus and CXL device: Total Latency = Device (CDAT) Latency + Dev to Switch Link Latency + Switch (CDAT) Latency + Switch to HB Link Latency + Generic Port Latency Min Bandwidth = Min bandwidth for link bandwidth between CXL device to CXL switch, CXL device CDAT bandwidth, CXL switch CDAT bandwidth, CXL switch to HB bandwidth, and Generic Port Bandwidth. Signed-off-by: Dave Jiang <dave.jiang@intel.com> --- drivers/cxl/cxlpci.h | 1 + drivers/cxl/port.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+)