From patchwork Wed Jun 29 18:15:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Fu Wei Fu X-Patchwork-Id: 71197 Delivered-To: patch@linaro.org Received: by 10.140.28.4 with SMTP id 4csp2294790qgy; Wed, 29 Jun 2016 11:17:49 -0700 (PDT) X-Received: by 10.66.134.172 with SMTP id pl12mr13874456pab.66.1467224267207; Wed, 29 Jun 2016 11:17:47 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l17si5448961pfa.42.2016.06.29.11.17.46; Wed, 29 Jun 2016 11:17:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752056AbcF2SRf (ORCPT + 5 others); Wed, 29 Jun 2016 14:17:35 -0400 Received: from mx1.redhat.com ([209.132.183.28]:48123 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752053AbcF2SRb (ORCPT ); Wed, 29 Jun 2016 14:17:31 -0400 Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id BC3226315E; Wed, 29 Jun 2016 18:17:24 +0000 (UTC) Received: from rei-ayanami.redhat.com (vpn1-4-13.pek2.redhat.com [10.72.4.13]) by int-mx13.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u5TIG89i019803; Wed, 29 Jun 2016 14:17:17 -0400 From: fu.wei@linaro.org To: rjw@rjwysocki.net, lenb@kernel.org, daniel.lezcano@linaro.org, tglx@linutronix.de, marc.zyngier@arm.com, hanjun.guo@linaro.org Cc: linux-arm-kernel@lists.infradead.org, linaro-acpi@lists.linaro.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, rruigrok@codeaurora.org, harba@codeaurora.org, cov@codeaurora.org, timur@codeaurora.org, graeme.gregory@linaro.org, al.stone@linaro.org, jcm@redhat.com, wei@redhat.com, arnd@arndb.de, wim@iguana.be, catalin.marinas@arm.com, will.deacon@arm.com, Suravee.Suthikulpanit@amd.com, leo.duran@amd.com, Fu Wei Subject: [PATCH v6 09/10] clocksource/drivers/arm_arch_timer: Add GTDT support for memory-mapped timer Date: Thu, 30 Jun 2016 02:15:52 +0800 Message-Id: <1467224153-22873-10-git-send-email-fu.wei@linaro.org> In-Reply-To: <1467224153-22873-1-git-send-email-fu.wei@linaro.org> References: <1467224153-22873-1-git-send-email-fu.wei@linaro.org> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.68 on 10.5.11.26 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Wed, 29 Jun 2016 18:17:25 +0000 (UTC) Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org From: Fu Wei The patch add memory-mapped timer register support by using the information provided by the new GTDT driver of ACPI. Signed-off-by: Fu Wei --- drivers/clocksource/arm_arch_timer.c | 131 ++++++++++++++++++++++++++++++++++- 1 file changed, 130 insertions(+), 1 deletion(-) -- 2.5.5 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 1382a49..683d691 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -849,7 +849,132 @@ CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem", arch_timer_mem_init); #ifdef CONFIG_ACPI_GTDT -/* Initialize per-processor generic timer */ +static struct gt_timer_data __init *arch_timer_mem_get_timer( + struct gt_block_data *gt_blocks) +{ + struct gt_block_data *gt_block = gt_blocks; + struct gt_timer_data *best_frame = NULL; + void __iomem *cntctlbase; + u32 cnttidr; + int i; + + /* + * According to ARMv8 Architecture Reference Manual(ARM), + * the size of CNTCTLBase frame of memory-mapped timer + * is SZ_4K(Offset 0x000 – 0xFFF). + */ + cntctlbase = ioremap(gt_block->cntctlbase_phy, SZ_4K); + if (!cntctlbase) { + pr_err("Can't map CNTCTLBase\n"); + return NULL; + } + cnttidr = readl_relaxed(cntctlbase + CNTTIDR); + + /* + * Try to find a virtual capable frame. Otherwise fall back to a + * physical capable frame. + */ + for (i = 0; i < gt_block->timer_count; i++) { + int n; + u32 cntacr; + + n = gt_block->timer[i].frame_nr; + + /* Try enabling everything, and see what sticks */ + cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT | + CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT; + writel_relaxed(cntacr, cntctlbase + CNTACR(n)); + cntacr = readl_relaxed(cntctlbase + CNTACR(n)); + + if ((cnttidr & CNTTIDR_VIRT(n)) && + !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) { + best_frame = >_block->timer[i]; + arch_timer_mem_use_virtual = true; + break; + } + + if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT)) + continue; + + best_frame = >_block->timer[i]; + } + iounmap(cntctlbase); + + return best_frame; +} + +static int __init arch_timer_mem_acpi_init(u32 timer_count) +{ + struct gt_block_data *gt_blocks; + struct gt_timer_data *gt_timer; + void __iomem *timer_cntbase; + int ret = -EINVAL; + int timer_irq; + + /* + * If we have some Platform Timer Structures, + * try to find and register a memory-mapped timer. + * If not, just return. + */ + if (!timer_count) + return 0; + + if (arch_timers_present & ARCH_MEM_TIMER) { + pr_warn("memory-mapped timer already initialized, skipping\n"); + return 0; + } + arch_timers_present |= ARCH_MEM_TIMER; + /* + * before really check all the Platform Timer Structures, + * we assume they are GT block, and allocate memory for them. + * We will free these memory once we finish the initialization. + */ + gt_blocks = kcalloc(timer_count, sizeof(*gt_blocks), GFP_KERNEL); + if (!gt_blocks) + return -ENOMEM; + + if (gtdt_arch_timer_mem_init(gt_blocks)) { + gt_timer = arch_timer_mem_get_timer(gt_blocks); + if (!gt_timer) { + pr_err("Failed to get mem timer info.\n"); + goto error; + } + + if (arch_timer_mem_use_virtual) + timer_irq = gt_timer->virt_irq; + else + timer_irq = gt_timer->irq; + if (!timer_irq) { + pr_err("Frame missing %s irq", + arch_timer_mem_use_virtual ? "virt" : "phys"); + goto error; + } + + /* + * According to ARMv8 Architecture Reference Manual(ARM), + * the size of CNTBaseN frames of memory-mapped timer + * is SZ_4K(Offset 0x000 – 0xFFF). + */ + timer_cntbase = ioremap(gt_timer->cntbase_phy, SZ_4K); + if (!timer_cntbase) { + pr_err("Can't map CntBase.\n"); + goto error; + } + arch_counter_base = timer_cntbase; + ret = arch_timer_mem_register(timer_cntbase, timer_irq); + if (ret) { + iounmap(timer_cntbase); + arch_counter_base = NULL; + pr_err("Failed to register mem timer.\n"); + } + } + +error: + kfree(gt_blocks); + return ret; +} + +/* Initialize per-processor generic timer and memory-mapped timer(if present) */ static int __init arch_timer_acpi_init(struct acpi_table_header *table) { int timer_count; @@ -875,6 +1000,10 @@ static int __init arch_timer_acpi_init(struct acpi_table_header *table) /* Get the frequency from CNTFRQ */ arch_timer_detect_rate(NULL, NULL); + + if (arch_timer_mem_acpi_init(timer_count)) + pr_err("Failed to initialize memory-mapped timer, skipping\n"); + arch_timer_init(); return 0;