From patchwork Sun Jan 4 10:55:12 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjun Guo X-Patchwork-Id: 42719 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wg0-f71.google.com (mail-wg0-f71.google.com [74.125.82.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 368B020A5F for ; Sun, 4 Jan 2015 10:57:00 +0000 (UTC) Received: by mail-wg0-f71.google.com with SMTP id k14sf3842806wgh.10 for ; Sun, 04 Jan 2015 02:56:59 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=jAca8k8CDtTZe4fDLzyDbxZQj1LZCnr8ESLvIURUv6w=; b=Sm7ckiLoCAOz/+ouoAVEmDpRjyr2I68bHnVN1YrH7xX+PpNwgrKb/7j9F3SrUoRL8p r8ai0qjdGgi/WIes3zsuS8BFn32/hjXJJjEusWrxa0fT7wkzgb40tivlIiyW34NdeoSX kmHc6TBzR+0C1PWIh+siZruV7UryfC8848+r8nlfOULrI73uICRXbeOnLL+4PPS4JNM5 V0Vgo4K/iCtS+8Pre8ZROFScPhB5/3j6QTc/YGCTQICc/FarNCWyAzx31phT4NcaskJg HWctEuK3IzMzqC5JepefgCO/rVqBSrnZ2n80DyFaO3xuuapo45vEUEccCCAR2ST5bqBM /SKA== X-Gm-Message-State: ALoCoQl8qjvh8WplGo5Ue9oFBPLRIAQfg1FnBFQhH0rxLMHEcWg+wxydEaMOwUERoSHpZ1x1YzLb X-Received: by 10.152.10.233 with SMTP id l9mr9681646lab.0.1420369019455; Sun, 04 Jan 2015 02:56:59 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.6.130 with SMTP id b2ls1082698laa.27.gmail; Sun, 04 Jan 2015 02:56:59 -0800 (PST) X-Received: by 10.152.23.164 with SMTP id n4mr84258434laf.77.1420369019117; Sun, 04 Jan 2015 02:56:59 -0800 (PST) Received: from mail-lb0-f179.google.com (mail-lb0-f179.google.com. [209.85.217.179]) by mx.google.com with ESMTPS id gl8si58010746lbc.60.2015.01.04.02.56.59 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sun, 04 Jan 2015 02:56:59 -0800 (PST) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.179 as permitted sender) client-ip=209.85.217.179; Received: by mail-lb0-f179.google.com with SMTP id z11so16308810lbi.24 for ; Sun, 04 Jan 2015 02:56:59 -0800 (PST) X-Received: by 10.112.41.234 with SMTP id i10mr87397601lbl.25.1420369018994; Sun, 04 Jan 2015 02:56:58 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.9.200 with SMTP id c8csp619161lbb; Sun, 4 Jan 2015 02:56:58 -0800 (PST) X-Received: by 10.66.181.136 with SMTP id dw8mr139866581pac.117.1420369016738; Sun, 04 Jan 2015 02:56:56 -0800 (PST) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id pb4si45214320pdb.139.2015.01.04.02.56.55; Sun, 04 Jan 2015 02:56:56 -0800 (PST) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752981AbbADK4o (ORCPT + 27 others); Sun, 4 Jan 2015 05:56:44 -0500 Received: from mail-pa0-f44.google.com ([209.85.220.44]:49952 "EHLO mail-pa0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752961AbbADK4l (ORCPT ); Sun, 4 Jan 2015 05:56:41 -0500 Received: by mail-pa0-f44.google.com with SMTP id et14so26742542pad.17 for ; Sun, 04 Jan 2015 02:56:40 -0800 (PST) X-Received: by 10.70.91.67 with SMTP id cc3mr137128658pdb.76.1420369000602; Sun, 04 Jan 2015 02:56:40 -0800 (PST) Received: from localhost ([180.150.148.224]) by mx.google.com with ESMTPSA id ob4sm51383771pdb.48.2015.01.04.02.56.38 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Sun, 04 Jan 2015 02:56:39 -0800 (PST) From: Hanjun Guo To: Catalin Marinas , "Rafael J. Wysocki" , Olof Johansson , Arnd Bergmann , Mark Rutland , Grant Likely , Will Deacon Cc: Lorenzo Pieralisi , Graeme Gregory , Sudeep Holla , Jon Masters , Jason Cooper , Marc Zyngier , Bjorn Helgaas , Mark Brown , Rob Herring , Robert Richter , Randy Dunlap , Charles.Garcia-Tobin@arm.com, phoenix.liyi@huawei.com, Timur Tabi , suravee.suthikulpanit@amd.com, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linaro-acpi@lists.linaro.org, Hanjun Guo Subject: [PATCH v6 11/17] ACPI / processor: Make it possible to get CPU hardware ID via GICC Date: Sun, 4 Jan 2015 18:55:12 +0800 Message-Id: <1420368918-5086-12-git-send-email-hanjun.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1420368918-5086-1-git-send-email-hanjun.guo@linaro.org> References: <1420368918-5086-1-git-send-email-hanjun.guo@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: hanjun.guo@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.179 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Introduce a new function map_gicc_mpidr() to allow MPIDRs to be obtained from the GICC Structure introduced by ACPI 5.1. MPIDR is the CPU hardware ID as local APIC ID on x86 platform, so we use MPIDR not the GIC CPU interface ID to identify CPUs. Tested-by: Suravee Suthikulpanit Signed-off-by: Hanjun Guo --- arch/arm64/include/asm/acpi.h | 29 +++++++++++++++++++++++++++++ arch/arm64/kernel/acpi.c | 1 - drivers/acpi/processor_core.c | 37 +++++++++++++++++++++++++++++++++++++ 3 files changed, 66 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h index c82d4a1..639bb2a 100644 --- a/arch/arm64/include/asm/acpi.h +++ b/arch/arm64/include/asm/acpi.h @@ -12,6 +12,8 @@ #ifndef _ASM_ACPI_H #define _ASM_ACPI_H +#include + /* Basic configuration for ACPI */ #ifdef CONFIG_ACPI #define acpi_strict 1 /* No out-of-spec workarounds on ARM64 */ @@ -45,6 +47,33 @@ static inline void enable_acpi(void) acpi_noirq = 0; } +/* MPIDR value provided in GICC structure is 64 bits, but the + * existing apic_id (CPU hardware ID) using in acpi processor + * driver is 32-bit, to conform to the same datatype we need + * to repack the GICC structure MPIDR. + * + * Only 32 bits of MPIDR are used: + * + * Bits [0:7] Aff0; + * Bits [8:15] Aff1; + * Bits [16:23] Aff2; + * Bits [32:39] Aff3; + */ +static inline u32 pack_mpidr(u64 mpidr) +{ + return (u32) ((mpidr & 0xff00000000) >> 8) | mpidr; +} + +/* + * The ACPI processor driver for ACPI core code needs this macro + * to find out this cpu was already mapped (mapping from CPU hardware + * ID to CPU logical ID) or not. + * + * cpu_logical_map(cpu) is the mapping of MPIDR and the logical cpu, + * and MPIDR is the cpu hardware ID we needed to pack. + */ +#define cpu_physical_id(cpu) pack_mpidr(cpu_logical_map(cpu)) + /* * It's used from ACPI core in kdump to boot UP system with SMP kernel, * with this check the ACPI core will not override the CPU index diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c index c01bf7f..e8bb9eb 100644 --- a/arch/arm64/kernel/acpi.c +++ b/arch/arm64/kernel/acpi.c @@ -24,7 +24,6 @@ #include #include -#include #include #include diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c index 02e4839..e634b14 100644 --- a/drivers/acpi/processor_core.c +++ b/drivers/acpi/processor_core.c @@ -64,6 +64,38 @@ static int map_lsapic_id(struct acpi_subtable_header *entry, return 0; } +/* + * On ARM platform, MPIDR value is the hardware ID as apic ID + * on Intel platforms + */ +static int map_gicc_mpidr(struct acpi_subtable_header *entry, + int device_declaration, u32 acpi_id, int *mpidr) +{ + struct acpi_madt_generic_interrupt *gicc = + container_of(entry, struct acpi_madt_generic_interrupt, header); + + if (!(gicc->flags & ACPI_MADT_ENABLED)) + return -ENODEV; + + /* In the GIC interrupt model, logical processors are + * required to have a Processor Device object in the DSDT, + * so we should check device_declaration here + */ + if (device_declaration && (gicc->uid == acpi_id)) { + /* + * Only bits [0:7] Aff0, bits [8:15] Aff1, bits [16:23] Aff2 + * and bits [32:39] Aff3 are meaningful, so pack the Affx + * fields into a single 32 bit identifier to accommodate the + * acpi processor drivers. + */ + *mpidr = ((gicc->arm_mpidr & 0xff00000000) >> 8) + | gicc->arm_mpidr; + return 0; + } + + return -EINVAL; +} + static int map_madt_entry(int type, u32 acpi_id) { unsigned long madt_end, entry; @@ -99,6 +131,9 @@ static int map_madt_entry(int type, u32 acpi_id) } else if (header->type == ACPI_MADT_TYPE_LOCAL_SAPIC) { if (!map_lsapic_id(header, type, acpi_id, &phys_id)) break; + } else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT) { + if (!map_gicc_mpidr(header, type, acpi_id, &phys_id)) + break; } entry += header->length; } @@ -131,6 +166,8 @@ static int map_mat_entry(acpi_handle handle, int type, u32 acpi_id) map_lsapic_id(header, type, acpi_id, &phys_id); else if (header->type == ACPI_MADT_TYPE_LOCAL_X2APIC) map_x2apic_id(header, type, acpi_id, &phys_id); + else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT) + map_gicc_mpidr(header, type, acpi_id, &phys_id); exit: kfree(buffer.pointer);