From patchwork Sun Sep 29 03:32:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Zhan X-Patchwork-Id: 831305 Received: from szxga07-in.huawei.com (szxga07-in.huawei.com [45.249.212.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0ADF817C8B; Sun, 29 Sep 2024 03:38:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.35 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727581111; cv=none; b=F07JGn8vPPlIYYb9Kk/z1kvb2RUQsmFJgRu7w8Esib/hWC31RXFSTGOkBkpF8JeDOGoGI88/ITQm81CIN1BKg5TZ90c4gAe+7IGmkQuMUe3YkiSN6YuXzm+aaXoGHEHKMBpUiqO9XURHZTGWoD+C/p0mQxJ6RXyRiU3R3kEe5N4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727581111; c=relaxed/simple; bh=9VkY50E8QK4yXq60zaRNmqSImq1PPvd/e3dCjlpe4XI=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=MtJMaZCpnKMXY6sTzFFdRZOp3mJJlXwoXIicOSI71Dm9PlC5g2qQQbyzOqKfbICnlrapAglq7F1cjO6HO7sKYSeC99PbbuuWaxc2SlzdMtTwfb/3JdMVEWUkLRFrfBmbwlrgPTaK1DL3K15Kd/Wuywelz1rIDEyImkzZKaIuWH4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=hisilicon.com; spf=pass smtp.mailfrom=hisilicon.com; arc=none smtp.client-ip=45.249.212.35 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=hisilicon.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=hisilicon.com Received: from mail.maildlp.com (unknown [172.19.162.112]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4XGVJM3X62z1SBPs; Sun, 29 Sep 2024 11:37:23 +0800 (CST) Received: from dggpeml500019.china.huawei.com (unknown [7.185.36.137]) by mail.maildlp.com (Postfix) with ESMTPS id 31673140157; Sun, 29 Sep 2024 11:38:16 +0800 (CST) Received: from localhost.localdomain (10.90.30.45) by dggpeml500019.china.huawei.com (7.185.36.137) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Sun, 29 Sep 2024 11:38:15 +0800 From: Jie Zhan To: , , , , CC: , , , , , , , , , , , Subject: [PATCH v4 0/2] cppc_cpufreq: Rework ->get() error handling when cores are idle Date: Sun, 29 Sep 2024 11:32:12 +0800 Message-ID: <20240929033214.1039485-1-zhanjie9@hisilicon.com> X-Mailer: git-send-email 2.30.0 Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: dggems703-chm.china.huawei.com (10.3.19.180) To dggpeml500019.china.huawei.com (7.185.36.137) CPPC feedback counters can be unchanged or 0 when cores are idle, e.g. clock-gated or power-gated. In such case, get the latest desired perf for calculating frequency. Also, the HiSilicon CPPC workaround can now be removed as it can be handled by the common code. --- v4: - Some additional comments as suggested. No functions changes. v3: - Merge patch 1 & 2, tidy up the logic, and reduce duplicate code - Return 0 in cppc_perf_from_fbctrs() if the feedback counters are unchanged rather than return a cached desired perf - Return early in cppc_scale_freq_workfn() if the feedback counters are unchanged v2: - Try reading the lastest desired perf first before using the cached one - Do the same handling logic when feedback counters are unchanged - Remove hisilicon workaround Discussions: v1: https://lore.kernel.org/all/20240819035147.2239767-1-zhanjie9@hisilicon.com/ v2: https://lore.kernel.org/all/20240912072231.439332-1-zhanjie9@hisilicon.com/ v3: https://lore.kernel.org/all/20240919084552.3591400-1-zhanjie9@hisilicon.com/ Jie Zhan (2): cppc_cpufreq: Use desired perf if feedback ctrs are 0 or unchanged cppc_cpufreq: Remove HiSilicon CPPC workaround drivers/cpufreq/cppc_cpufreq.c | 128 ++++++++++++--------------------- 1 file changed, 46 insertions(+), 82 deletions(-)