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[0/7] Enumerate HDM Decoder registers

Message ID 20210407222625.320177-1-ben.widawsky@intel.com
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Series Enumerate HDM Decoder registers | expand

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Ben Widawsky April 7, 2021, 10:26 p.m. UTC 
The arbiter of a Host-managed Device Memory (HDM) region is an "HDM Decoder".
An HDM decoder is defined in the Compute eXpress Link (CXL) specification as
hardware that handles the routing of memory ranges controlled by CXL devices in
a linear, or interleaved fashion.

HDM decoders are not specific to CXL devices and therefore live in a different
part of the MMIO space for CXL *components*. The CXL component registers are
found and mapped in a similar way to the device registers and so a lot of this
series is refactoring to try to easily add the new register block type.

Management of HDM decoders is not handled in this series. This work is the
foundation for the eventual integration with libnvdimm. That integration will
enable CXL persistent and volatile capacities to be managed by Linux and gain
use of all the related existing infrastructure.

These patches go on top of the reworks and improvements recently submitted by
Dan [1].

[1]: https://lore.kernel.org/linux-cxl/161728744224.2474040.12854720917440712854.stgit@dwillia2-desk3.amr.corp.intel.com/T/#t

Ben Widawsky (7):
  cxl/mem: Use dev instead of pdev->dev
  cxl/mem: Split creation from mapping in probe
  cxl/mem: Move register locator logic into reg setup
  cxl/mem: Get rid of @cxlm.base
  cxl/mem: Move device register setup
  cxl/mem: Create a helper to setup device regs
  cxl: Add HDM decoder capbilities

 drivers/cxl/core.c |  73 +++++++++++++++
 drivers/cxl/cxl.h  |  48 ++++++++++
 drivers/cxl/mem.c  | 225 +++++++++++++++++++++++++++------------------
 drivers/cxl/mem.h  |   2 -
 drivers/cxl/pci.h  |   1 +
 5 files changed, 260 insertions(+), 89 deletions(-)


base-commit: 24ca2d6ff18cc59c14c0aff65025b0cc11a72722