From patchwork Fri Nov 30 15:47:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 152567 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp3814005ljp; Fri, 30 Nov 2018 07:50:21 -0800 (PST) X-Google-Smtp-Source: AFSGD/XHb+l+VU7e8fliYTHr9B9zw+F2In/24mhUJO/PmP9sSmmc9iOLjOWyqegM88oTFrSx/drb X-Received: by 2002:a62:cd44:: with SMTP id o65mr6062099pfg.222.1543593020905; Fri, 30 Nov 2018 07:50:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1543593020; cv=none; d=google.com; s=arc-20160816; b=HTBidOL+O8i3C/PBTpNP8eIajHosB4kecN1yeHBCem5IvbhrrTWLiLq3vsVxSSV2Zd tDmBWtjJ3NNZuRouRe5iXx5cS5ZOHDvcJTG41fgJuXtRTRIXa78W55pDF1PAsaXxhqvA VOtm0g6NoF5DGxy+COMLEHYNvSRc/TnP6aIODdNCRzLDl3JuVj+/2HF46gCx0Xv3SMRd 0LIqlfb47wHbmavpQL1zTWp2KaKg+Rooh3iKbGmi9zVuYvk/mz2mVz7e5KiqlFV6S7Z6 DER/F/6OWH5utznlZpoSL+vsG7r4ad+qj9yhIbJIpRPnn89RaV8F5e+Z6ih9kxrwHVdG /bHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from; bh=UtQL/epaB/86cglJUQna7XnbjUR40ekmJ7hjSjjxJGc=; b=li/P0xMG8FGD0omv7DypLEteAIpeuBsH+G93Y6qr0bfU5G5r1ExLDZKMgayw9jHPy+ r6zstmYATU+0ZuG5kSgITglkZTF6Cc6TqmKy0xpS7G12BhL5Gu2upBU4hnpusEDRWM0q Gsnmm7qRtPiMBxlVWeLhgOjXJ1rYfgjRji83Dxl/C9OT/tyD2YgyQzZVN6CjyMgFOWg5 qc8zS96qlM70tjl1o4TklFKThgse6KK7k3FOVqAvspS+FFzC8N8Pi7rtHquAT5t2+nKZ qpcBl8NaZYnRJUefcihFOACmexvsz6wJmBZEyBASP92TNL0XS4kk1dbHPKpVSAa/riQp iVww== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 35si5352047pgn.278.2018.11.30.07.50.20; Fri, 30 Nov 2018 07:50:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726127AbeLADAF (ORCPT + 9 others); Fri, 30 Nov 2018 22:00:05 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:55110 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727520AbeLADAE (ORCPT ); Fri, 30 Nov 2018 22:00:04 -0500 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 29D941A345CF; Fri, 30 Nov 2018 23:49:19 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.408.0; Fri, 30 Nov 2018 23:49:12 +0800 From: Shameer Kolothum To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 0/4] arm64 SMMUv3 PMU driver with IORT support Date: Fri, 30 Nov 2018 15:47:47 +0000 Message-ID: <20181130154751.28580-1-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org This adds a driver for the SMMUv3 PMU into the perf framework. It includes an IORT update to support PM Counter Groups. This is based on the initial work done by Neil Leeder[1] SMMUv3 PMCG devices are named as smmuv3_pmcg_ where is the physical page address of the SMMU PMCG. For example, the PMCG at 0xff88840000 is named smmuv3_pmcg_ff88840 Usage example: For common arch supported events: perf stat -e smmuv3_pmcg_ff88840/transaction,filter_enable=1, filter_span=1,filter_stream_id=0x42/ -a netperf For IMP DEF events: perf stat -e smmuv3_pmcg_ff88840/event=id/ -a netperf This is sanity tested on a HiSilicon platform that requires a quirk to run it properly. As per HiSilicon erratum #162001800, PMCG event counter registers (SMMU_PMCG_EVCNTRn) on HiSilicon Hip08 platforms are read only and this prevents the software from setting the initial period on event start. Unfortunately we were a bit late in the cycle to detect this issue and now require software workaround for this. Patch #4 is added to this series to provide a workaround for this issue. Further testing on supported platforms are very much welcome. v4 ---> v5 -IORT code is modified to pass the option/quirk flags to the driver through platform_data (patch #4), based on Robin's comments. -Removed COMPILE_TEST (patch #2). v3 --> v4 -Addressed comments from Jean and Robin. -Merged dma config callbacks as per Lorenzo's comments(patch #1). -Added handling of Global(Counter0) filter settings mode(patch #2). -Added patch #4 to address HiSilicon erratum #162001800 - v2 --> v3 -Addressed comments from Robin. -Removed iort helper function to retrieve the PMCG reference smmu. -PMCG devices are now named using the base address v1 --> v2 - Addressed comments from Robin. - Added an helper to retrieve the associated smmu dev and named PMUs to make the association visible to user. - Added MSI support for overflow irq [1]https://www.spinics.net/lists/arm-kernel/msg598591.html Neil Leeder (2): acpi: arm64: add iort support for PMCG perf: add arm64 smmuv3 pmu driver Shameer Kolothum (2): perf/smmuv3: Add MSI irq support perf/smmuv3_pmu: Enable HiSilicon Erratum 162001800 quirk drivers/acpi/arm64/iort.c | 127 +++++-- drivers/perf/Kconfig | 9 + drivers/perf/Makefile | 1 + drivers/perf/arm_smmuv3_pmu.c | 859 ++++++++++++++++++++++++++++++++++++++++++ include/linux/acpi_iort.h | 3 + 5 files changed, 975 insertions(+), 24 deletions(-) create mode 100644 drivers/perf/arm_smmuv3_pmu.c -- 2.7.4 Reviewed-by: Robin Murphy