From patchwork Wed Nov 29 14:14:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 120011 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp3111763qgn; Wed, 29 Nov 2017 06:16:53 -0800 (PST) X-Google-Smtp-Source: AGs4zMZBqeZHj3UNBY5Sykm4iq/WchNsH+aBhhADsHTxYQpCg/fr75qvH57gMcwfrfPvMhwATqro X-Received: by 10.84.164.165 with SMTP id w34mr3015197pla.73.1511965013340; Wed, 29 Nov 2017 06:16:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1511965013; cv=none; d=google.com; s=arc-20160816; b=aR/W5BKzdh8OWJX5s6x6trI2Ine10o2hmJXanVVD1jMNuzxze6stIXXKqJX/d2r0S8 2b8UQkYJOzGZVb8ZztkRZpe17SNB/fB5okiye/VEO6SLKn1I+zJBj6V9IwI4ZIco11eC QGi+y6bGztt4gGlpB3QrHKt0UR92bvjZd9IFWczPKPnuGxK/w6/lP6Yosl0tPwT4lpqK BnVua05knO7QWG06d86Fr3UQ07k1BsmhHZ4Wg5hSPWF+crcn/DOJjG9jsht7kMySZ4BE LLUY49NF9kwIcLKNo8INq4Rv1SVurifcJfnrjhtbZbvjHMS0MEpYA+hEl1vTtyNdINDM VWcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=1Ej5nSAS6ffGooPtsPuYjj01lb2ggtWPGkX1An4WW/w=; b=dFKXq6J1J5d2Qw016oHioBxv34DTeJvbnIRghJvZVd2qaBRolBBXaRkM0GhI0ofnQJ p8oaxDh3KHEEH8DlO1NhIVqX22hesOfKCEwQJf+ZTS+hZ3afUbal6KVIl82u9qH652r0 elBS73vINSIR/qlA++zRC+wq4aGu1+amGRCtbna3e9jCgwpAzwiw7n9e2Hnewg+Qk+l1 zQudeaKDDXUPV+8DC6F0Gv3Pdq4E3f66pdriIwj+qg1JvVW+/Z8t2qzcnpGZlseVOkWo F/UC1yGN6+1KsFtdRdbjFi/776TTOMLdH4u+CJbflPMKfpyrWYZ2n4RdSyJqVvceUJDi eWMw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f4si1318931pgo.205.2017.11.29.06.16.53; Wed, 29 Nov 2017 06:16:53 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932761AbdK2OQv (ORCPT + 7 others); Wed, 29 Nov 2017 09:16:51 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:46508 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S932687AbdK2OQr (ORCPT ); Wed, 29 Nov 2017 09:16:47 -0500 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id C1E3F8B80A67; Wed, 29 Nov 2017 22:16:32 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.361.1; Wed, 29 Nov 2017 22:16:25 +0800 From: Shameer Kolothum To: , , , , CC: , , , , , , , , Shameer Kolothum Subject: [PATCH v10 0/3] iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI) Date: Wed, 29 Nov 2017 14:14:46 +0000 Message-ID: <20171129141449.120316-1-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org On certain HiSilicon platforms (hip06/hip07) the GIC ITS and PCIe RC deviates from the standard implementation and this breaks PCIe MSI functionality when SMMU is enabled. The HiSilicon erratum 161010801 describes this limitation of certain HiSilicon platforms to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements an ACPI based quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. To implement this quirk, the following changes are incorporated: 1. Added a generic helper function to IORT code to retrieve and reserve the associated ITS base address from a device IORT node. The function has a check for smmu model to determine whether the platform requires the HW MSI reservation or not. 2. Added smmu node entries and explicitly disabled them in hip06/hip07 dts files so that users are warned about the non-DT support for this erratum. Changelog: v9 --> v10 Addressed comments: -Moved smmu model check to iort helper function to selectively apply the msi reservation which will make the fn call generic from iommu-dma. -Removed PCI blacklisting patch, instead added smmu nodes(disabled) with comments to hip06/hip07 dts file. v8 --> v9 -Thanks to Marc, fixed IORT helper function to reserve the ITS translater region only. -Removed the DT support for MSI reservation and blacklisted HiSilicon PCIe controllers on DT based systems when SMMUv3 is enabled. v7 --> v8 Addressed comments from Rob and Lorenzo: -Modified to use DT compatible string for errata. -Changed logic to retrieve the msi-parent for DT case. v6 --> v7 Addressed request from Will to add DT support for the erratum: - added bt binding - add of_iommu_msi_get_resv_regions() New arm64 silicon errata entry Rename iort_iommu_{its->msi}_get_resv_regions v5 --> v6 Addressed comments from Robin and Lorenzo: -No change to patch#1 . -Reverted v5 patch#2 as this might break the platforms where this quirk is not applicable. Provided a generic function in iommu code and added back the quirk implementation in SMMU v3 driver(patch#3) v4 --> v5 Addressed comments from Robin and Lorenzo: -Added a comment to make it clear that, for now, only straightforward HW topologies are handled while reserving ITS regions(patch #1). v3 --> v4 Rebased on 4.13-rc1. Addressed comments from Robin, Will and Lorenzo: -As suggested by Robin, moved the ITS msi reservation into iommu_dma_get_resv_regions(). -Added its_count != resv region failure case(patch #1). v2 --> v3 Addressed comments from Lorenzo and Robin: -Removed dev_is_pci() check in smmuV3 driver. -Don't treat device not having an ITS mapping as an error in iort helper function. v1 --> v2 -patch 2/2: Invoke iort helper fn based on fwnode type(acpi). RFCv2 -->PATCH -Incorporated Lorenzo's review comments. RFC v1 --> RFC v2 Based on Robin's review comments, -Removed the generic erratum framework. -Using IORT/MADT tables to retrieve the ITS base addr instead of vendor specific CSRT table. Shameer Kolothum (3): ACPI/IORT: Add msi address regions reservation helper iommu/dma: Add HW MSI(GICv3 ITS) address regions reservation arm64:dts:hisilicon Disable hisilicon smmu node on hip06/hip07 arch/arm64/boot/dts/hisilicon/hip06.dtsi | 55 +++++++++++++ arch/arm64/boot/dts/hisilicon/hip07.dtsi | 24 ++++++ drivers/acpi/arm64/iort.c | 133 ++++++++++++++++++++++++++++++- drivers/iommu/dma-iommu.c | 8 +- drivers/irqchip/irq-gic-v3-its.c | 3 +- include/linux/acpi_iort.h | 7 +- 6 files changed, 224 insertions(+), 6 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html