From patchwork Fri Oct 6 14:04:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 115069 Delivered-To: patch@linaro.org Received: by 10.80.163.170 with SMTP id s39csp1411069edb; Fri, 6 Oct 2017 07:08:04 -0700 (PDT) X-Google-Smtp-Source: AOwi7QAucE8St8IBOXn6L3d43XrqEfqjrD+Yk9J4fCgJw3f/g5MZPzL6QasQjhlNDQlPH/MioIy6 X-Received: by 10.99.100.70 with SMTP id y67mr2124681pgb.161.1507298884350; Fri, 06 Oct 2017 07:08:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507298884; cv=none; d=google.com; s=arc-20160816; b=Hht0+icmcxneFWsqcJlzT3oF6rkM7VMnD3CWuHbLMLFttRUQrrrqRJEZpq7a1qeGHg aACMPRxMrP0qvNzNK0ZrlkUZxNiXkwv0/oE8mMIdwxxptbZ/9qxEUTI8reOf5xTCYk7b dutl6Faivq+Fdo4tsAv9QeTlRoJoaKloC985kCPpVJXT+OltBFAEgEUY+4IzZB29+Qze 8XTSzySgRRO2jQJ9qXpFIfOyxLO1pBH5hSIYtfmXRcrFDapiJItlY4QJxxUsTEtMPB5q DQQCkQ3VP3Yykc3Y6R6YKzwxA16zo4I+HutGUsWno/5plv42fVhY8IrqprW9f3NsLPoE 4AfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=TaqDBBVBMYC1JdYxgiMcsvXyDtS89I++7JyfNV0e6WA=; b=GckFe0bjgSkVHjke5myUgjDXsvodeqJgNN3o9u3uoHfAA+ZZFxsNZvqmAYwiWzr9l5 /k2hyRG+QY5pK8n6aa8W6Yf4mm6Uc0WsiWuFLXJ9lMjqRcky6S+7E245lgxAXorac419 2hZYcA4FyZ6LBJSlNLrA7UTQdspOLMGxxH1Dcrq/6KbGqxdOiGCJnR1y4tpvW+3torp4 +7MSiMdrwb7lHfVcTaLPpddBWUpXwQN4h/FZcvQt9pk7iAd4zbhwWr6XYDcNSWHjOOlo hQriwr4VH0azM8+CNzbOdspE7HlSl15Gpgt8u6BYB87ddn+pblqhb97u/R5tnxK8hhC0 2eJg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r145si1303201pfr.567.2017.10.06.07.08.03; Fri, 06 Oct 2017 07:08:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751527AbdJFOIB (ORCPT + 7 others); Fri, 6 Oct 2017 10:08:01 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:7501 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751720AbdJFOH7 (ORCPT ); Fri, 6 Oct 2017 10:07:59 -0400 Received: from 172.30.72.58 (EHLO DGGEMS403-HUB.china.huawei.com) ([172.30.72.58]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DIO33379; Fri, 06 Oct 2017 22:07:53 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.301.0; Fri, 6 Oct 2017 22:07:17 +0800 From: Shameer Kolothum To: , , , , , , , CC: , , , , , , , , , Shameer Kolothum Subject: [PATCH v9 0/4] iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI) Date: Fri, 6 Oct 2017 15:04:46 +0100 Message-ID: <20171006140450.89652-1-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090206.59D78E39.0173, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 00ed57d9c26fc93e5398d5573cf0cf9c Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org On certain HiSilicon platforms (hip06/hip07) the GIC ITS and PCIe RC deviates from the standard implementation and this breaks PCIe MSI functionality when SMMU is enabled. The HiSilicon erratum 161010801 describes this limitation of certain HiSilicon platforms to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements an ACPI and DT based quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. To implement this quirk, the following changes are incorporated: 1. Added a generic helper function to IORT code to retrieve the associated ITS base address from a device IORT node. 2. Added a generic helper function to of iommu code to retrieve the associated msi controller base address from for a PCI RC msi-mapping and also platform device msi-parent. 3. Blacklisted HiSilicon PCIe controllers on DT based hip06/hip07 platforms when SMMUv3 is enabled as there is no DT based solution for this as of now. Changelog: v8 --> v9 -Thanks to Marc, fixed IORT helper function to reserve the ITS translater region only. -Removed the DT support for MSI reservation and blacklisted HiSilicon PCIe controllers on DT based systems when SMMUv3 is enabled. v7 --> v8 Addressed comments from Rob and Lorenzo: -Modified to use DT compatible string for errata. -Changed logic to retrieve the msi-parent for DT case. v6 --> v7 Addressed request from Will to add DT support for the erratum: - added bt binding - add of_iommu_msi_get_resv_regions() New arm64 silicon errata entry Rename iort_iommu_{its->msi}_get_resv_regions v5 --> v6 Addressed comments from Robin and Lorenzo: -No change to patch#1 . -Reverted v5 patch#2 as this might break the platforms where this quirk is not applicable. Provided a generic function in iommu code and added back the quirk implementation in SMMU v3 driver(patch#3) v4 --> v5 Addressed comments from Robin and Lorenzo: -Added a comment to make it clear that, for now, only straightforward HW topologies are handled while reserving ITS regions(patch #1). v3 --> v4 Rebased on 4.13-rc1. Addressed comments from Robin, Will and Lorenzo: -As suggested by Robin, moved the ITS msi reservation into iommu_dma_get_resv_regions(). -Added its_count != resv region failure case(patch #1). v2 --> v3 Addressed comments from Lorenzo and Robin: -Removed dev_is_pci() check in smmuV3 driver. -Don't treat device not having an ITS mapping as an error in iort helper function. v1 --> v2 -patch 2/2: Invoke iort helper fn based on fwnode type(acpi). RFCv2 -->PATCH -Incorporated Lorenzo's review comments. RFC v1 --> RFC v2 Based on Robin's review comments, -Removed the generic erratum framework. -Using IORT/MADT tables to retrieve the ITS base addr instead of vendor specific CSRT table. Shameer Kolothum (4): ACPI/IORT: Add msi address regions reservation helper iommu/dma: Add a helper function to reserve HW MSI address regions for IOMMU drivers iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 PCI: hisi: blacklist hip06/hip07 controllers behind SMMUv3 drivers/acpi/arm64/iort.c | 97 ++++++++++++++++++++++++++++++++++++++-- drivers/iommu/arm-smmu-v3.c | 27 ++++++++--- drivers/iommu/dma-iommu.c | 20 +++++++++ drivers/irqchip/irq-gic-v3-its.c | 3 +- drivers/pci/dwc/pcie-hisi.c | 12 +++++ include/linux/acpi_iort.h | 7 ++- include/linux/dma-iommu.h | 7 +++ 7 files changed, 163 insertions(+), 10 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html