From patchwork Thu Sep 14 12:57:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 112552 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp714425qgf; Thu, 14 Sep 2017 06:00:47 -0700 (PDT) X-Google-Smtp-Source: ADKCNb5a9C2gxCqDNVs9VxG129NY9kiIN4QAjN/evGAfUpwGbTZXyTM0Q/+giL+14R/QZ2r3LvrA X-Received: by 10.101.75.201 with SMTP id p9mr21695244pgr.281.1505394047171; Thu, 14 Sep 2017 06:00:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1505394047; cv=none; d=google.com; s=arc-20160816; b=ve6we+tYPmYEPtof8cpMKreD0dNVcdWQ5t0TFQ6s3uFjOsUgcx3mBsJgn5lNcplOPB trmECtaadulTjpD30Cp2k+at8R6+0fjCwn3UMhFM66qPjCPRNTYfddm8p+Jus0f8rAu/ YTBoc3EIRx3i+uYj3/e3e211ffairK1uRMIpeF4s5EhIAH8dkyvis6X5Ly6J3YFW96yx tuLZN8LgZzKUHHRwRCjNjgWPk6iB06ttkjvXngkfVzJ0zPilZsI8S4JZ4OI5cl8+sEEh 3YyXJlbGl9Ez9aenp4SUxxazDUn9MopRNH40861EWZIBWyzToVNuS4X8LbN6p8HtKRZb HGEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=hauAKviYYkEcW45Uv+QgDCkVTXfuTV/CEDw/J01YDhA=; b=u7gM5xpnHcqpplMQQi7iquylMPui5BPctMgBUb1sMb9Vb03nsCdeqwcEgf90THBh+Z Qx0WG8W391k2CjDLHCyNyqdnkGunqpXpHvKT8per5HqRgh49OWM5ANSL33dwnOUE3oUR NmMiqiOr4hpsCgvvsdGcORDlDSpImht3Zf6njtEViFag6bs4UNsdr0OCYQsGUwT7Kvwd xBTaJV+s3cF3DTsIPu27ujvWnLpc0gNckGMY4XLA1uVrk5SaFIOaMy/zQRzfauHOLd1Q XIjyeEU4O0hSUz25k/Dq9PqQQXEMW//34kuNFmOC3eG6lcMl9LJDQqmqtfdHOluud/Bs FVWQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e92si12526571plk.739.2017.09.14.06.00.46; Thu, 14 Sep 2017 06:00:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751255AbdINNAq (ORCPT + 7 others); Thu, 14 Sep 2017 09:00:46 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:6058 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751131AbdINNAp (ORCPT ); Thu, 14 Sep 2017 09:00:45 -0400 Received: from 172.30.72.58 (EHLO DGGEMS413-HUB.china.huawei.com) ([172.30.72.58]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DHH33779; Thu, 14 Sep 2017 21:00:40 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.212.247.163) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.301.0; Thu, 14 Sep 2017 21:00:30 +0800 From: Shameer Kolothum To: , , , , , , , CC: , , , , , , , , , , Shameer Kolothum Subject: [PATCH v7 0/5] iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI) Date: Thu, 14 Sep 2017 13:57:51 +0100 Message-ID: <20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.212.247.163] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.59BA7D79.003A, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: b9f2301d5d55a745764a794f01ffd5e1 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org On certain HiSilicon platforms (hip06/hip07) the GIC ITS and PCIe RC deviates from the standard implementation and this breaks PCIe MSI functionality when SMMU is enabled. The HiSilicon erratum 161010801 describes this limitation of certain HiSilicon platforms to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements an ACPI and DT based quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. To implement this quirk, the following changes are incorporated: 1. Added a generic helper function to IORT code to retrieve the associated ITS base address from a device IORT node. 2. Added a generic helper function to of iommu code to retrieve the associated msi controller base address from for a PCI RC msi-mapping and also platform device msi-parent. 3. Added quirk to SMMUv3 to retrieve the HW ITS address and replace the default SW MSI reserve address based on the IORT SMMU model or DT bindings. Changelog: v6 --> v7 Addressed request from Will to add DT support for the erratum: - added bt binding - add of_iommu_msi_get_resv_regions() New arm64 silicon errata entry Rename iort_iommu_{its->msi}_get_resv_regions v5 --> v6 Addressed comments from Robin and Lorenzo: -No change to patch#1 . -Reverted v5 patch#2 as this might break the platforms where this quirk is not applicable. Provided a generic function in iommu code and added back the quirk implementation in SMMU v3 driver(patch#3) v4 --> v5 Addressed comments from Robin and Lorenzo: -Added a comment to make it clear that, for now, only straightforward HW topologies are handled while reserving ITS regions(patch #1). v3 --> v4 Rebased on 4.13-rc1. Addressed comments from Robin, Will and Lorenzo: -As suggested by Robin, moved the ITS msi reservation into iommu_dma_get_resv_regions(). -Added its_count != resv region failure case(patch #1). v2 --> v3 Addressed comments from Lorenzo and Robin: -Removed dev_is_pci() check in smmuV3 driver. -Don't treat device not having an ITS mapping as an error in iort helper function. v1 --> v2 -patch 2/2: Invoke iort helper fn based on fwnode type(acpi). RFCv2 -->PATCH -Incorporated Lorenzo's review comments. RFC v1 --> RFC v2 Based on Robin's review comments, -Removed the generic erratum framework. -Using IORT/MADT tables to retrieve the ITS base addr instead of vendor specific CSRT table. John Garry (2): Doc: iommu/arm-smmu-v3: Add workaround for HiSilicon erratum 161010801 iommu/of: Add msi address regions reservation helper Shameer Kolothum (3): ACPI/IORT: Add msi address regions reservation helper iommu/dma: Add a helper function to reserve HW MSI address regions for IOMMU drivers iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 Documentation/arm64/silicon-errata.txt | 1 + .../devicetree/bindings/iommu/arm,smmu-v3.txt | 3 + drivers/acpi/arm64/iort.c | 96 ++++++++++++++++- drivers/iommu/arm-smmu-v3.c | 28 ++++- drivers/iommu/dma-iommu.c | 19 ++++ drivers/iommu/of_iommu.c | 117 +++++++++++++++++++++ drivers/irqchip/irq-gic-v3-its.c | 3 +- include/linux/acpi_iort.h | 7 +- include/linux/dma-iommu.h | 7 ++ include/linux/of_iommu.h | 10 ++ 10 files changed, 281 insertions(+), 10 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html