From patchwork Wed Aug 9 10:07:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 109698 Delivered-To: patch@linaro.org Received: by 10.140.95.78 with SMTP id h72csp646359qge; Wed, 9 Aug 2017 03:08:51 -0700 (PDT) X-Received: by 10.99.163.26 with SMTP id s26mr6981633pge.232.1502273331603; Wed, 09 Aug 2017 03:08:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1502273331; cv=none; d=google.com; s=arc-20160816; b=eHdweJKvhoc4B6VSD/odNJHD+X7JSC8xCDWXe8GYJEx+/tJT06iGtmMsc4qKgvqTcy tYHwaWNA0cm4vD2jAwIU1EeJ5/b8kWDtSqXO1o6eKxpzMMuDqzUHHmPKA2HWCc3bmUqZ P/Ji5MJEvQtI8M/jHkoUt06pUweV0CLwI3b+lc1T558Nf1J+CQDLzTZBAuujlNwxZuib 3iPoRYc6bvt4XRQtRGRkkCna84tb6XLb///O2qU2kRrtfd6rOpYJWUV0Mn1aQ53J+vid zYpNr4PjRgsEqqVkznp+fnh7CMCnRj0U39qVCyW6g/6//7kyzoc7wFT8wNb4/M1Io3J4 GUNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=Xe1Ek2RD0Zyj3bZQ1+as+r0X6MI9On4G4xCsk2G+2cQ=; b=I3K6+iJlu7YVGLpfu2WbFgUWxn7YSHymUMcRp+C2yxaR6mAFKUiiH2G/CnG6r95Fgf UOGG1xdj95sOhJYPGtzOzMvEiONZ5NDV+oGG5xPrIOuBqp+D26DGMiQADC4Ca2seFUx2 /5oscMov31BUkup2KuBn9ESnTPVs4gC4ASXDUdbELcNao9bUs+apuTzUjV29So4YdmBV UB1XcIN4enhI+Jq2Zi/Etb5efpJS2qK7kx5NULuwokSUAHTlwQ9wyDCWzT7AzOtVBPZM oLoBX3oE39KeNX/lb0I3+zbAT3NPergv3Mo6L1bfOZJ6A8WB7sMSvrJjGZE+1iaPFKPq 6ljw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v7si2201572pgb.858.2017.08.09.03.08.51; Wed, 09 Aug 2017 03:08:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753029AbdHIKIt (ORCPT + 7 others); Wed, 9 Aug 2017 06:08:49 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:3477 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752836AbdHIKIs (ORCPT ); Wed, 9 Aug 2017 06:08:48 -0400 Received: from 172.30.72.59 (EHLO DGGEMS414-HUB.china.huawei.com) ([172.30.72.59]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DEU02352; Wed, 09 Aug 2017 18:08:39 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.301.0; Wed, 9 Aug 2017 18:08:28 +0800 From: Shameer Kolothum To: , , , , , CC: , , , , , , , , , Shameer Kolothum Subject: [PATCH v6 0/3] iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI) Date: Wed, 9 Aug 2017 11:07:12 +0100 Message-ID: <20170809100715.870516-1-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A010202.598ADF2D.0012, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: d16d0daa229f32bfcecbd95469117d37 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org On certain HiSilicon platforms (Hip06/Hip07) the GIC ITS and PCIe RC deviates from the standard implementation and this breaks PCIe MSI functionality when SMMU is enabled. The HiSilicon erratum 161010801 describes this limitation of certain HiSilicon platforms to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. To implement this quirk, the following changes are incorporated: 1. Added a generic helper function to IORT code to retrieve and reserve the HW ITS address regions. 2. Added quirk to SMMUv3 to reserve HW ITS address regions based on IORT SMMUv3 model with the help of a generic iommu helper function. Thanks, Shameer Changelog: v5 --> v6 Addressed comments from Robin and Lorenzo: -No change to patch#1 . -Reverted v5 patch#2 as this might break the platforms where this quirk is not applicable. Provided a generic function in iommu code and added back the quirk implementation in SMMU v3 driver(patch#3) v4 --> v5 Addressed comments from Robin and Lorenzo: -Added a comment to make it clear that, for now, only straightforward HW topologies are handled while reserving ITS regions(patch #1). v3 --> v4 Rebased on 4.13-rc1. Addressed comments from Robin, Will and Lorenzo: -As suggested by Robin, moved the ITS msi reservation into iommu_dma_get_resv_regions(). -Added its_count != resv region failure case(patch #1). v2 --> v3 Addressed comments from Lorenzo and Robin: -Removed dev_is_pci() check in smmuV3 driver. -Don't treat device not having an ITS mapping as an error in iort helper function. v1 --> v2 -patch 2/2: Invoke iort helper fn based on fwnode type(acpi). RFCv2 -->PATCH -Incorporated Lorenzo's review comments. RFC v1 --> RFC v2 Based on Robin's review comments, -Removed the generic erratum framework. -Using IORT/MADT tables to retrieve the ITS base addr instead of vendor specific CSRT table. Shameer Kolothum (3): ACPI/IORT: Add ITS address regions reservation helper iommu/dma: Add a helper function to reserve HW MSI address regions for IOMMU drivers iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 drivers/acpi/arm64/iort.c | 95 ++++++++++++++++++++++++++++++++++++++-- drivers/iommu/arm-smmu-v3.c | 27 +++++++++--- drivers/iommu/dma-iommu.c | 19 ++++++++ drivers/irqchip/irq-gic-v3-its.c | 3 +- include/linux/acpi_iort.h | 7 ++- include/linux/dma-iommu.h | 7 +++ 6 files changed, 148 insertions(+), 10 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html