From patchwork Mon Jun 19 15:44:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 105862 Delivered-To: patch@linaro.org Received: by 10.182.29.35 with SMTP id g3csp913123obh; Mon, 19 Jun 2017 08:47:37 -0700 (PDT) X-Received: by 10.98.16.220 with SMTP id 89mr25636200pfq.210.1497887257300; Mon, 19 Jun 2017 08:47:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1497887257; cv=none; d=google.com; s=arc-20160816; b=1EG1jwtpq9NgxLRt63jbyCgxKxjBNj5jSbjwHWINiZ6uJDqZCYOHxcxcNCgiBEetw7 QnVORENVVQd4QNl1XpTedzTjt9KZ7eJhsHmbiGuwLJMlvghvmWydZ5zXTtrwfg8SFTVM 1DdwjNZWY2FEwC8djal/WUYwl+PDawteliR3ylSk/IglH9+qdePr/jspZwcG8oCVyLin TB4gH1vs40bQOWsRWnbzZ2jgKNyGZnXWngzfu2hpvuyp7j9t/YNGz4X5pvAtvalVesIz LQ5M2DDAWe+EmGQVOUD4X0cpXYd/5frGBqAaKETZs2XHrjkFFfnbCT9J2ka/LrYmFRd5 Qhcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=UG2VD5UHGNBS22GiVzbiyuqnI++cSK3G/JZI7hNQUFQ=; b=roo2qwx2hHq3XntYGZqOhu4h3ysv1TRAYE2bqAFGVskJum//wHjnfOAHN/Vqwy7rmJ q50o2/sZcKm/C233gNkBuK4bCkuzcn1e3P7SFeMGTzNhy75LyN1Oin6MbBOF7Uj5LhxA g6T4Ws4eBNwah2nl9S5vF9W25mycVysqU0wCdIn0z9sc4/UzQ1SHF6s1Fs1vTi4gi2bX 7fzcr+2/snppbiJ9dfGca4ZvndPmVwVvBujOsb2zrald2rByUZAuQTsa5gUYkSlAHD7W lcPa/jjMl5U42I5WC2uPpk3E7FtOEFekruac1D/EHxYGQfd82je2tWS02Fe8JlCL233Z wl/A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s8si4701600plj.27.2017.06.19.08.47.37; Mon, 19 Jun 2017 08:47:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753672AbdFSPrV (ORCPT + 8 others); Mon, 19 Jun 2017 11:47:21 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:8344 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753370AbdFSPrU (ORCPT ); Mon, 19 Jun 2017 11:47:20 -0400 Received: from 172.30.72.57 (EHLO DGGEML401-HUB.china.huawei.com) ([172.30.72.57]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APQ38244; Mon, 19 Jun 2017 23:47:09 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by DGGEML401-HUB.china.huawei.com (10.3.17.32) with Microsoft SMTP Server id 14.3.301.0; Mon, 19 Jun 2017 23:47:00 +0800 From: shameer To: , , , , , CC: , , , , , , , , , shameer Subject: [PATCH v2 0/2] iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI) Date: Mon, 19 Jun 2017 16:44:58 +0100 Message-ID: <20170619154500.92336-1-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.5947F1FD.0211, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 23e4fd4152cc63372e72863cce66356a Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org On certain HiSilicon platforms (Hip06/Hip07) the GIC ITS and PCIe RC deviates from the standard implementation and this breaks PCIe MSI functionality when SMMU is enabled. The HiSilicon erratum 161010801 describes this limitation of certain HiSilicon platforms to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements a ACPI table based quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. To implement this quirk, the following changes are incorporated: 1. Added a generic helper function to IORT code to retrieve and reserve the HW ITS address regions. 2. Added quirk to SMMUv3 to reserve HW ITS address regions based on IORT SMMUv3 model. This is based on the following patches: 1. https://patchwork.kernel.org/patch/9740733/ 2. https://patchwork.kernel.org/patch/9730491/ Thanks, Shameer Changelog: v1 --> v2 -patch 2/2: Invoke iort helper fn based on fwnode type(acpi). RFCv2 -->PATCH -Incorporated Lorenzo's review comments. RFC v1 --> RFC v2 Based on Robin's review comments, -Removed the generic erratum framework. -Using IORT/MADT tables to retrieve the ITS base addr instead of vendor specific CSRT table. shameer (2): acpi:iort: Add an IORT helper function to reserve HW ITS address regions for IOMMU drivers iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 drivers/acpi/arm64/iort.c | 91 ++++++++++++++++++++++++++++++++++++++-- drivers/iommu/arm-smmu-v3.c | 29 ++++++++++--- drivers/irqchip/irq-gic-v3-its.c | 3 +- include/linux/acpi_iort.h | 7 +++- 4 files changed, 120 insertions(+), 10 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html