From patchwork Fri Oct 13 07:09:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hanjun Guo X-Patchwork-Id: 115703 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp415628qgn; Fri, 13 Oct 2017 00:23:55 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCk+sUqUbDJOo03j2/e8/AC265ze3Kif8H2bUtyRdNWG38dxBUC6u2WvZFrDDTIu1Hi0HBH X-Received: by 10.98.157.18 with SMTP id i18mr596912pfd.120.1507879434966; Fri, 13 Oct 2017 00:23:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507879434; cv=none; d=google.com; s=arc-20160816; b=omrg1gb/CyrIGLvhAIV2pTXkil3pkz9IzPEgs3G7Xpcp+lZKL/d1v474jzhvrITvS0 i3xtqZFh6d3NVNEWAFbZrxsuLpPNfdg63zcOA9/0p0LR3Be/UMBtvsQqb+AX/i5W76UT YDdP1DTDbsJ68XCbieSFAZI3PI8//ZhfC3rRLaX6X+ZbNpL0eoRR95vKrJufGYislIlr pWZn0z54bmm7ZHSHCqRcz4S4wFfluTSZTg54qpYM3DifaHc0ynXsokMiG9/NLVwRDZ9U zJElZG7i51CYDSXbYHbyOsrdyUxtOpAuCJjzO2wOcHc6t+t6RLtmtlmxFbnRbcjf2umd d2rA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=JEh4DL/irlVsszkjNHAtdZbAxX9aGZJGqCG8Ko0Mu1s=; b=U7aR9Hc59ClCe+o2lR2j+5YUtT+vvj7U+L/EHWBzl2kYAgOC+e+Nn9BS2iMFfWofkF TcdM7FCmk64bNziLXb901Ucah4obs4JgaOVS6ED1WEc891WA0AJUgHeSLMTWKk+vSDco eNytWAJLyxqiTESTbUNkuOHSdpaGrp19hQr3dhnhDa9CpbyhddT2b3EULhZ+CtQPquN9 l3vmfCQ1N/Gkhr9vDArIsvCVkyvAODyV93U2+DfMrT6PIBrpKg5qjgfFCtP6vbOmu0ZE /OEz8sN4G0xzVfdT+nryXJLUCttLzoezbSMgbOLIi6Y4sDveIMNKdzSh17oCJ8j/yFIE mBRQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v7si228476pfd.123.2017.10.13.00.23.54; Fri, 13 Oct 2017 00:23:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-acpi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-acpi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752029AbdJMHXx (ORCPT + 7 others); Fri, 13 Oct 2017 03:23:53 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:7997 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750722AbdJMHXw (ORCPT ); Fri, 13 Oct 2017 03:23:52 -0400 Received: from 172.30.72.59 (EHLO DGGEMS402-HUB.china.huawei.com) ([172.30.72.59]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DIZ07858; Fri, 13 Oct 2017 15:20:09 +0800 (CST) Received: from linux-ibm.site (10.175.102.37) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.301.0; Fri, 13 Oct 2017 15:17:48 +0800 From: Hanjun Guo To: Lorenzo Pieralisi , Robin Murphy CC: Marc Zyngier , "Rafael J. Wysocki" , , , , Hanjun Guo Subject: [PATCH v2 0/4] IORT SMMUv3 MSI support Date: Fri, 13 Oct 2017 15:09:46 +0800 Message-ID: <1507878590-51066-1-git-send-email-guohanjun@huawei.com> X-Mailer: git-send-email 1.7.12.4 MIME-Version: 1.0 X-Originating-IP: [10.175.102.37] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.59E06929.00B6, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: f294e7a7d4a6210aae78910dab1ea326 Sender: linux-acpi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org From: Hanjun Guo IORT revision C introduced SMMUv3 MSI support for control interrupts, which introduced a device ID mapping index to retrieve the dev ID and ITS parent, adding its support in this patch set, please refer to each patch for detail commit message. This patch set is based on Lorenzo's v2 clearup/rework for iort: https://www.spinics.net/lists/arm-kernel/msg611089.html Tested on D05 without breakage, and SMMU msi function is OK on hip08 platform, this version is intented for merge. v1 -> v2: - Rewrote commit message by Lorenzo to remove some wrong message; - Split patch 3/4 in v1 into two by Lorenzo to make the logic clearer; - Drop acpica patch but use the ACPICA version as a guard for function iort_get_id_mapping_index() in case acpica for linux kernel is not ready (patch for acpica iasl was merged already). RFC v2 -> v1: - Drop RFC tag; - return the index value directly from iort_get_id_mapping_index() then make the logic simple in iort_node_map_id(); - To make sure ID mapping index is only ignored if all interrupts are GSIV based - Sqursh part of the patch 4 to patch 3 RFC v1 -> RFC v2: - Introduce a new API iort_set_device_domain() to find the MSI domain for an SMMUv3 (or any other IORT table node) to reduce the complex of doing that via acpi_configure_pmsi_domain(). Hanjun Guo (3): ACPI/IORT: Look up IORT node through struct fwnode_handle pointer ACPI/IORT: Enable special index ITS group mappings for IORT nodes ACPI/IORT: Add SMMUv3 specific special index mapping handling Lorenzo Pieralisi (1): ACPI/IORT: Enable SMMUv3/PMCG IORT MSI domain set-up drivers/acpi/arm64/iort.c | 159 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 153 insertions(+), 6 deletions(-) -- 1.7.12.4 -- To unsubscribe from this list: send the line "unsubscribe linux-acpi" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html