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[209.132.180.67]) by mx.google.com with ESMTP id hz7si949967pbc.52.2014.05.16.02.07.51; Fri, 16 May 2014 02:07:51 -0700 (PDT) Received-SPF: none (google.com: linux-pm-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756538AbaEPJHq (ORCPT + 12 others); Fri, 16 May 2014 05:07:46 -0400 Received: from mail-pa0-f46.google.com ([209.85.220.46]:39989 "EHLO mail-pa0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755616AbaEPJHo (ORCPT ); Fri, 16 May 2014 05:07:44 -0400 Received: by mail-pa0-f46.google.com with SMTP id kq14so2288724pab.5 for ; Fri, 16 May 2014 02:07:44 -0700 (PDT) X-Received: by 10.68.137.193 with SMTP id qk1mr16395469pbb.155.1400231264140; Fri, 16 May 2014 02:07:44 -0700 (PDT) Received: from localhost ([122.167.105.65]) by mx.google.com with ESMTPSA id be7sm32114062pad.9.2014.05.16.02.07.39 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 16 May 2014 02:07:43 -0700 (PDT) From: Viresh Kumar To: rjw@rjwysocki.net Cc: linaro-kernel@lists.linaro.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, arvind.chauhan@arm.com, swarren@nvidia.com, nicolas.pitre@linaro.org, swarren@wwwdotorg.org, dianders@chromium.org, linux@arm.linux.org.uk, thomas.abraham@linaro.org, pdeschrijver@nvidia.com, Viresh Kumar Subject: [PATCH V2 3/3] cpufreq: Tegra: implement intermediate frequency callbacks Date: Fri, 16 May 2014 14:37:19 +0530 Message-Id: X-Mailer: git-send-email 2.0.0.rc2 In-Reply-To: <9e1ed1bf8c3610709436fe5ef8df3a63856f8f5c.1400230695.git.viresh.kumar@linaro.org> References: <9e1ed1bf8c3610709436fe5ef8df3a63856f8f5c.1400230695.git.viresh.kumar@linaro.org> In-Reply-To: References: Sender: linux-pm-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: viresh.kumar@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.175 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Tegra had always been switching to intermediate frequency (pll_p_clk) since ever. CPUFreq core has better support for handling notifications for these frequencies and so we can adapt Tegra's driver to it. Signed-off-by: Viresh Kumar Tested-by: Stephen Warren --- drivers/cpufreq/tegra-cpufreq.c | 81 +++++++++++++++++++---------------------- 1 file changed, 38 insertions(+), 43 deletions(-) diff --git a/drivers/cpufreq/tegra-cpufreq.c b/drivers/cpufreq/tegra-cpufreq.c index 6e774c6..10b29ec 100644 --- a/drivers/cpufreq/tegra-cpufreq.c +++ b/drivers/cpufreq/tegra-cpufreq.c @@ -46,9 +46,33 @@ static struct clk *pll_x_clk; static struct clk *pll_p_clk; static struct clk *emc_clk; -static int tegra_cpu_clk_set_rate(unsigned long rate) +static unsigned int +tegra_get_intermediate(struct cpufreq_policy *policy, unsigned int index) { - int ret; + return clk_get_rate(pll_p_clk); +} + +static int +tegra_target_intermediate(struct cpufreq_policy *policy, unsigned int frequency) +{ + return clk_set_parent(cpu_clk, pll_p_clk); +} + +static int tegra_target(struct cpufreq_policy *policy, unsigned int index) +{ + unsigned long rate = freq_table[index].frequency; + int ret = 0; + + /* + * Vote on memory bus frequency based on cpu frequency + * This sets the minimum frequency, display or avp may request higher + */ + if (rate >= 816000) + clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */ + else if (rate >= 456000) + clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */ + else + clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */ /* * Take an extra reference to the main pll so it doesn't turn @@ -56,12 +80,6 @@ static int tegra_cpu_clk_set_rate(unsigned long rate) */ clk_prepare_enable(pll_x_clk); - ret = clk_set_parent(cpu_clk, pll_p_clk); - if (ret) { - pr_err("Failed to switch cpu to clock pll_p\n"); - goto out; - } - if (rate == clk_get_rate(pll_p_clk)) goto out; @@ -72,36 +90,11 @@ static int tegra_cpu_clk_set_rate(unsigned long rate) } ret = clk_set_parent(cpu_clk, pll_x_clk); - if (ret) { + if (ret) pr_err("Failed to switch cpu to clock pll_x\n"); - goto out; - } out: clk_disable_unprepare(pll_x_clk); - return ret; -} - -static int tegra_target(struct cpufreq_policy *policy, unsigned int index) -{ - unsigned long rate = freq_table[index].frequency; - int ret = 0; - - /* - * Vote on memory bus frequency based on cpu frequency - * This sets the minimum frequency, display or avp may request higher - */ - if (rate >= 816000) - clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */ - else if (rate >= 456000) - clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */ - else - clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */ - - ret = tegra_cpu_clk_set_rate(rate * 1000); - if (ret) - pr_err("cpu-tegra: Failed to set cpu frequency to %lu kHz\n", - rate); return ret; } @@ -137,16 +130,18 @@ static int tegra_cpu_exit(struct cpufreq_policy *policy) } static struct cpufreq_driver tegra_cpufreq_driver = { - .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, - .verify = cpufreq_generic_frequency_table_verify, - .target_index = tegra_target, - .get = cpufreq_generic_get, - .init = tegra_cpu_init, - .exit = tegra_cpu_exit, - .name = "tegra", - .attr = cpufreq_generic_attr, + .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, + .verify = cpufreq_generic_frequency_table_verify, + .get_intermediate = tegra_get_intermediate, + .target_intermediate = tegra_target_intermediate, + .target_index = tegra_target, + .get = cpufreq_generic_get, + .init = tegra_cpu_init, + .exit = tegra_cpu_exit, + .name = "tegra", + .attr = cpufreq_generic_attr, #ifdef CONFIG_PM - .suspend = cpufreq_generic_suspend, + .suspend = cpufreq_generic_suspend, #endif };