From patchwork Tue Dec 9 15:51:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 42061 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-lb0-f197.google.com (mail-lb0-f197.google.com [209.85.217.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id B762E25E75 for ; Tue, 9 Dec 2014 15:52:07 +0000 (UTC) Received: by mail-lb0-f197.google.com with SMTP id n15sf684929lbi.8 for ; Tue, 09 Dec 2014 07:52:06 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:mime-version:in-reply-to:references :date:message-id:subject:from:to:cc:content-type:sender:precedence :list-id:x-original-sender:x-original-authentication-results :mailing-list:list-post:list-help:list-archive:list-unsubscribe; bh=GCUvaggbXAC5ky7uzwAoFm94ZrFwYbvPZKmpMK+7BaQ=; b=Hu9Om408au3U0Zo34Qv3Zs0Sx60DRV85XVYPhrt5HNg3AQ3+Gw3QZ8ROp5TWrDP76f ix68XJtyewZ4HaMdYqodnrq4IPp0dZbdg/29eK5fivbG83VQ+26FSCkKaLhpHAc+L0tS ie3PWpl+aufVilIGxzfXl4L5A811+OFnmhwHV+O3f4O+Z9NgFMw2Hb1S06+8exoWBnUu PTuzSCOpiZpUP7hyP1mB+xQHo8ypor3NjB+40gUGIBpRmpc7YkP//bpcpmIl1xfvx30D nfE4m4Htgnt1It/cJvdQG9caR77e6EU07JD67Suxbn3NqQv2POqBA84dhdenhDDzu1o2 vbwA== X-Gm-Message-State: ALoCoQmQ2LLWyVmk+a5BIBwAbv6dZjRftygIhlmNr/O2e/CBov1y/Bb62o053yKSzbhWU7nY7NID X-Received: by 10.152.8.67 with SMTP id p3mr1549023laa.4.1418140326699; Tue, 09 Dec 2014 07:52:06 -0800 (PST) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.5.227 with SMTP id v3ls53544lav.91.gmail; Tue, 09 Dec 2014 07:52:06 -0800 (PST) X-Received: by 10.152.21.9 with SMTP id r9mr22839087lae.76.1418140326559; Tue, 09 Dec 2014 07:52:06 -0800 (PST) Received: from mail-lb0-f176.google.com (mail-lb0-f176.google.com. [209.85.217.176]) by mx.google.com with ESMTPS id ax5si1766542lbc.9.2014.12.09.07.52.06 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 09 Dec 2014 07:52:06 -0800 (PST) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.176 as permitted sender) client-ip=209.85.217.176; Received: by mail-lb0-f176.google.com with SMTP id p9so725260lbv.7 for ; Tue, 09 Dec 2014 07:52:06 -0800 (PST) X-Received: by 10.112.235.196 with SMTP id uo4mr22188018lbc.66.1418140326436; Tue, 09 Dec 2014 07:52:06 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.184.201 with SMTP id ew9csp770497lbc; Tue, 9 Dec 2014 07:52:04 -0800 (PST) X-Received: by 10.70.43.105 with SMTP id v9mr32249630pdl.158.1418140323794; Tue, 09 Dec 2014 07:52:03 -0800 (PST) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id qn8si2438338pab.101.2014.12.09.07.52.02 for ; Tue, 09 Dec 2014 07:52:03 -0800 (PST) Received-SPF: none (google.com: devicetree-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754286AbaLIPwB (ORCPT + 4 others); Tue, 9 Dec 2014 10:52:01 -0500 Received: from mail-oi0-f47.google.com ([209.85.218.47]:33687 "EHLO mail-oi0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754093AbaLIPwA (ORCPT ); Tue, 9 Dec 2014 10:52:00 -0500 Received: by mail-oi0-f47.google.com with SMTP id v63so576032oia.20 for ; Tue, 09 Dec 2014 07:51:59 -0800 (PST) MIME-Version: 1.0 X-Received: by 10.60.81.131 with SMTP id a3mr11659801oey.81.1418140319742; Tue, 09 Dec 2014 07:51:59 -0800 (PST) Received: by 10.182.56.162 with HTTP; Tue, 9 Dec 2014 07:51:59 -0800 (PST) In-Reply-To: <52c403454c3b8fc201abe7ac74cf657638479311.1417691389.git.viresh.kumar@linaro.org> References: <52c403454c3b8fc201abe7ac74cf657638479311.1417691389.git.viresh.kumar@linaro.org> Date: Tue, 9 Dec 2014 21:21:59 +0530 Message-ID: Subject: Re: [RFC] OPP: Redefine bindings to overcome shortcomings From: Viresh Kumar To: Rafael Wysocki , Arnd Bergmann , Rob Herring , Grant Likely , "olof@lixom.net" Cc: Lists linaro-kernel , "linux-pm@vger.kernel.org" , Nishanth Menon , Sudeep Holla , Stephen Boyd , "devicetree@vger.kernel.org" , santosh shilimkar , Mike Turquette , Abhilash Kesavan , Catalin Marinas , Thomas Abraham , "linux-arm-kernel@lists.infradead.org" , Thomas Petazzoni , Viresh Kumar Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: viresh.kumar@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.176 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , On 4 December 2014 at 16:44, Viresh Kumar wrote: > The shortcomings we are trying to solve here: > > - Some kind of compatibility string to probe the right cpufreq driver for > platforms, when multiple drivers are available. For example: how to choose > between cpufreq-dt and arm_big_little drivers. > > - Getting clock sharing information between CPUs. Single shared clock vs. > independent clock per core vs. shared clock per cluster. > > - Support for turbo modes > > - Other per OPP settings: transition latencies, disabled status, etc.? Some updates on the structure of bindings which I got up to with help of Arnd and Rob over IRC, have got better examples to show how things would look like: the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/power/opp.txt b/Documentation/devicetree/bindings/power/opp.txt index 74499e5033fc..8ae574b84650 100644 --- a/Documentation/devicetree/bindings/power/opp.txt +++ b/Documentation/devicetree/bindings/power/opp.txt @@ -1,9 +1,292 @@ -* Generic OPP Interface +Generic OPP (Operating Performance Points) Interface +---------------------------------------------------- SoCs have a standard set of tuples consisting of frequency and voltage pairs that the device will support per voltage domain. These are called Operating Performance Points or OPPs. +This documents defines OPP bindings with its required/optional properties. +OPPs can be defined for any device, this file uses CPU device as an example to +illustrate how to define OPPs. + +opp nodes and opp-lists + +- opp-listN: + List of nodes defining performance points. Following belong to the nodes + within the opp-lists. + + Required properties: + - frequency-kHz: Frequency in kHz + - voltage-uV: voltage in micro Volts + + Optional properties: + - turbo-mode: Marks the volt-freq pair as turbo pair. + - status: Marks the node enabled/disabled. + +- oppN: + Operating performance point node per device. Devices using it should have its + phandle in their "operating-points-v2" property. + + Required properties: + - compatible: allow OPPs to express their compatibility + - opp-list: phandle to opp-list defined above. + + Optional properties: + - clocks: Tuple of clock providers + - clock-names: Clock names + - opp-supply: phandle to the parent supply/regulator node + - voltage-tolerance: Specify the CPU voltage tolerance in percentage. + - clock-latency: Specify the possible maximum transition latency for clock, + in unit of nanoseconds. + +Example 1: Simple case of dual-core cortex A9-single cluster, sharing clock line. + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + operating-points-v2 = <&opp0>; + + opp0: opp0 { + compatible = "linux,cpu-dvfs"; + clocks = <&clk-controller 0>; + clock-names = "cpu"; + opp-supply = <&cpu-supply0>; + voltage-tolerance = <2>; /* percentage */ + clock-latency = <300000>; + opp-list = <&opplist0>; + + opplist0: opp-list0 { + entry00 { + frequency-kHz = <1000000>; + voltage-uV = <975000>; + status = "okay"; + }; + entry01 { + frequency-kHz = <1100000>; + voltage-uV = <1000000>; + status = "okay"; + }; + entry01 { + frequency-kHz = <1200000>; + voltage-uV = <1025000>; + status = "okay"; + turbo-mode; + }; + }; + }; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + operating-points-v2 = <&opp0>; + }; + }; +}; + +Example 2: Quad-core krait (All CPUs have independent clock lines but have same set of OPPs) + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "qcom,krait"; + reg = <0>; + next-level-cache = <&L2>; + operating-points-v2 = <&opp0>; + + opp0: opp0 { + compatible = "linux,cpu-dvfs"; + clocks = <&clk-controller 0>; + clock-names = "cpu"; + opp-supply = <&cpu-supply0>; + voltage-tolerance = <2>; /* percentage */ + clock-latency = <300000>; + opp-list = <&opplist0>; + + opplist0: opp-list0 { + entry00 { + frequency-kHz = <1000000>; + voltage-uV = <975000>; + status = "okay"; + }; + entry01 { + frequency-kHz = <1100000>; + voltage-uV = <1000000>; + status = "okay"; + }; + entry01 { + frequency-kHz = <1200000>; + voltage-uV = <1025000>; + status = "okay"; + turbo-mode; + }; + }; + }; + }; + + cpu@1 { + compatible = "qcom,krait"; + reg = <1>; + next-level-cache = <&L2>; + operating-points-v2 = <&opp1>; + + opp1: opp1 { + compatible = "linux,cpu-dvfs"; + clocks = <&clk-controller 1>; + clock-names = "cpu"; + opp-supply = <&cpu-supply1>; + voltage-tolerance = <2>; /* percentage */ + clock-latency = <300000>; + opp-list = <&opplist0>; + }; + }; + + cpu@2 { + compatible = "qcom,krait"; + reg = <2>; + next-level-cache = <&L2>; + operating-points-v2 = <&opp2>; + + opp2: opp2 { + compatible = "linux,cpu-dvfs"; + clocks = <&clk-controller 2>; + clock-names = "cpu"; + opp-supply = <&cpu-supply2>; + voltage-tolerance = <2>; /* percentage */ + clock-latency = <300000>; + opp-list = <&opplist0>; + }; + }; + + cpu@3 { + compatible = "qcom,krait"; + reg = <3>; + next-level-cache = <&L2>; + operating-points-v2 = <&opp3>; + + opp3: opp3 { + compatible = "linux,cpu-dvfs"; + clocks = <&clk-controller 3>; + clock-names = "cpu"; + opp-supply = <&cpu-supply3>; + voltage-tolerance = <2>; /* percentage */ + clock-latency = <300000>; + opp-list = <&opplist0>; + }; + }; + }; +}; + +Example 3: Multi-cluster system with separate clock line per cluster. + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + reg = <0>; + next-level-cache = <&L2>; + operating-points-v2 = <&opp0>; + + opp0: opp0 { + compatible = "linux,cpu-dvfs"; + clocks = <&clk-controller 0>; + clock-names = "cpu"; + opp-supply = <&cpu-supply0>; + voltage-tolerance = <2>; /* percentage */ + clock-latency = <300000>; + opp-list = <&opplist0>; + + opplist0: opp-list0 { + entry00 { + frequency-kHz = <1000000>; + voltage-uV = <975000>; + status = "okay"; + }; + entry01 { + frequency-kHz = <1100000>; + voltage-uV = <1000000>; + status = "okay"; + }; + entry01 { + frequency-kHz = <1200000>; + voltage-uV = <1025000>; + status = "okay"; + turbo-mode; + }; + }; + }; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + reg = <1>; + next-level-cache = <&L2>; + operating-points-v2 = <&opp0>; + }; + + cpu@100 { + compatible = "arm,cortex-a15"; + reg = <100>; + next-level-cache = <&L2>; + operating-points-v2 = <&opp1>; + + opp1: opp1 { + compatible = "linux,cpu-dvfs"; + clocks = <&clk-controller 1>; + clock-names = "cpu"; + opp-supply = <&cpu-supply1>; + voltage-tolerance = <2>; /* percentage */ + clock-latency = <400000>; + opp-list = <&opplist1>; + + opplist1: opp-list1 { + entry10 { + frequency-kHz = <1300000>; + voltage-uV = <1050000>; + status = "okay"; + }; + entry11 { + frequency-kHz = <1400000>; + voltage-uV = <1075000>; + status = "disabled"; + }; + entry12 { + frequency-kHz = <1500000>; + voltage-uV = <1100000>; + status = "okay"; + turbo-mode; + }; + }; + }; + }; + + cpu@101 { + compatible = "arm,cortex-a15"; + reg = <101>; + next-level-cache = <&L2>; + operating-points-v2 = <&opp1>; + }; + }; +}; + + + +Deprecated Bindings +------------------- + -- To unsubscribe from this list: send the line "unsubscribe devicetree" in