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[209.132.180.67]) by mx.google.com with ESMTP id tt1si18966580pbc.195.2015.06.19.19.24.25; Fri, 19 Jun 2015 19:24:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754054AbbFTCYY (ORCPT + 7 others); Fri, 19 Jun 2015 22:24:24 -0400 Received: from mail-pa0-f50.google.com ([209.85.220.50]:34841 "EHLO mail-pa0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753696AbbFTCYX (ORCPT ); Fri, 19 Jun 2015 22:24:23 -0400 Received: by pacyx8 with SMTP id yx8so96205592pac.2 for ; Fri, 19 Jun 2015 19:24:22 -0700 (PDT) X-Received: by 10.66.90.137 with SMTP id bw9mr37548522pab.52.1434767062888; Fri, 19 Jun 2015 19:24:22 -0700 (PDT) Received: from localhost ([122.167.70.98]) by mx.google.com with ESMTPSA id fk4sm12454554pbb.80.2015.06.19.19.24.21 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 19 Jun 2015 19:24:21 -0700 (PDT) Date: Sat, 20 Jun 2015 07:54:18 +0530 From: Viresh Kumar To: Rob Herring Cc: Stephen Boyd , Rafael Wysocki , "linaro-kernel@lists.linaro.org" , "linux-pm@vger.kernel.org" , Arnd Bergmann , Nishanth Menon , Mark Brown , Mike Turquette , Grant Likely , Olof Johansson , Sudeep Holla , "devicetree@vger.kernel.org" , Viswanath Puttagunta , Lucas Stach , Thomas Petazzoni , "linux-arm-kernel@lists.infradead.org" , Thomas Abraham , Abhilash Kesavan , Kevin Hilman , Santosh Shilimkar Subject: Re: [PATCH V7 2/3] OPP: Allow multiple OPP tables to be passed via DT Message-ID: <20150620022418.GB1955@linux> References: <263c128844f5a3c9280c8be71f6c9eb1869a5188.1433434659.git.viresh.kumar@linaro.org> <20150617133314.GB15153@linux> <55821F30.2090802@codeaurora.org> <20150618022543.GA28820@linux> <20150618025034.GB28820@linux> <20150619184747.GD22132@codeaurora.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: viresh.kumar@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.179 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , On 19-06-15, 13:52, Rob Herring wrote: > On Fri, Jun 19, 2015 at 1:47 PM, Stephen Boyd wrote: > > But isn't this being removed? If it is removed, feel free to add Sigh.. > > Reviewed-by: Stephen Boyd > Acked-by: Rob Herring Thanks. And here is the final Acked version.. ------------------------8<----------------------- From: Viresh Kumar Date: Thu, 30 Apr 2015 17:38:00 +0530 Subject: [PATCH] OPP: Allow multiple OPP tables to be passed via DT On some platforms (Like Qualcomm's SoCs), it is not decided until runtime on what OPPs to use. The OPP tables can be fixed at compile time, but which table to use is found out only after reading some efuses (sort of an prom) and knowing characteristics of the SoC. To support such platform we need to pass multiple OPP tables per device and hardware should be able to choose one and only one table out of those. Update operating-points-v2 bindings to support that. Reviewed-by: Stephen Boyd Acked-by: Rob Herring Signed-off-by: Viresh Kumar --- Documentation/devicetree/bindings/power/opp.txt | 60 +++++++++++++++++++++++++ 1 file changed, 60 insertions(+) -- To unsubscribe from this list: send the line "unsubscribe devicetree" in diff --git a/Documentation/devicetree/bindings/power/opp.txt b/Documentation/devicetree/bindings/power/opp.txt index 259bf00edf7d..3d5d32ca0f97 100644 --- a/Documentation/devicetree/bindings/power/opp.txt +++ b/Documentation/devicetree/bindings/power/opp.txt @@ -45,10 +45,21 @@ Devices supporting OPPs must set their "operating-points-v2" property with phandle to a OPP table in their DT node. The OPP core will use this phandle to find the operating points for the device. +Devices may want to choose OPP tables at runtime and so can provide a list of +phandles here. But only *one* of them should be chosen at runtime. This must be +accompanied by a corresponding "operating-points-names" property, to uniquely +identify the OPP tables. + If required, this can be extended for SoC vendor specfic bindings. Such bindings should be documented as Documentation/devicetree/bindings/power/-opp.txt and should have a compatible description like: "operating-points-v2-". +Optional properties: +- operating-points-names: Names of OPP tables (required if multiple OPP + tables are present), to uniquely identify them. The same list must be present + for all the CPUs which are sharing clock/voltage rails and hence the OPP + tables. + * OPP Table Node This describes the OPPs belonging to a device. This node can have following @@ -68,6 +79,8 @@ This describes the OPPs belonging to a device. This node can have following Missing property means devices have independent clock/voltage/current lines, but they share OPP tables. +- status: Marks the OPP table enabled/disabled. + * OPP Node @@ -396,3 +409,50 @@ Example 4: Handling multiple regulators }; }; }; + +Example 5: Multiple OPP tables + +/ { + cpus { + cpu@0 { + compatible = "arm,cortex-a7"; + ... + + cpu-supply = <&cpu_supply> + operating-points-v2 = <&cpu0_opp_table_slow>, <&cpu0_opp_table_fast>; + operating-points-names = "slow", "fast"; + }; + }; + + cpu0_opp_table_slow: opp_table_slow { + compatible = "operating-points-v2"; + status = "okay"; + opp-shared; + + opp00 { + opp-hz = <600000000>; + ... + }; + + opp01 { + opp-hz = <800000000>; + ... + }; + }; + + cpu0_opp_table_fast: opp_table_fast { + compatible = "operating-points-v2"; + status = "okay"; + opp-shared; + + opp10 { + opp-hz = <1000000000>; + ... + }; + + opp11 { + opp-hz = <1100000000>; + ... + }; + }; +};