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[82.33.25.158]) by mx.google.com with ESMTPSA id dn4sm4687808wib.18.2014.05.14.08.59.41 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 May 2014 08:59:42 -0700 (PDT) From: Daniel Thompson To: Jason Wessel , kgdb-bugreport@lists.sourceforge.net Cc: patches@linaro.org, linaro-kernel@lists.linaro.org, Daniel Thompson , linux-kernel@vger.kernel.org, John Stultz , Anton Vorontsov , Colin Cross , Dirk Behme , kernel-team@android.com, Russell King , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , "David A. Long" , Nicolas Pitre , Catalin Marinas , Frederic Weisbecker , Linus Walleij , Christoffer Dall , linux-arm-kernel@lists.infradead.org, kernel@stlinux.com, devicetree@vger.kernel.org, linux-serial@vger.kernel.org Subject: [RFC 8/8] arm: fiq: Hack FIQ routing backdoors into GIC and VIC Date: Wed, 14 May 2014 16:58:45 +0100 Message-Id: <1400083125-1464-9-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 1.9.0 In-Reply-To: <1400083125-1464-1-git-send-email-daniel.thompson@linaro.org> References: <1400083125-1464-1-git-send-email-daniel.thompson@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: daniel.thompson@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.182 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This is a hack to make it easy to check that the other interfaces in the patchset make sense. It needs to be replaced by code to get the interrupt controllers to expose FIQs. Unless a better option presents itself I plan to double up each interrupt source (so we get two virqs, one for regular interrupt and one for FIQ). This is what most of the prior art around FIQ in Linux has done in the past. Signed-off-by: Daniel Thompson --- arch/arm/boot/dts/stih416.dtsi | 2 +- arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 2 +- arch/arm/kernel/fiq.c | 39 +++++++++++++++++++++++++++++++++ drivers/irqchip/irq-gic.c | 27 +++++++++++++++++++++++ 4 files changed, 68 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index 78746d2..a288898 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -99,7 +99,7 @@ compatible = "st,asc"; status = "disabled"; reg = <0xfe531000 0x2c>; - interrupts = <0 210 0>; + interrupts = <0 210 0>, <0 210 0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_serial1>; clocks = <&CLK_SYSIN>; diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index ac870fb..fab2a40 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -140,7 +140,7 @@ v2m_serial0: uart@090000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x090000 0x1000>; - interrupts = <5>; + interrupts = <5>, <5>; clocks = <&v2m_oscclk2>, <&smbclk>; clock-names = "uartclk", "apb_pclk"; }; diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c index defbe85..efce321 100644 --- a/arch/arm/kernel/fiq.c +++ b/arch/arm/kernel/fiq.c @@ -41,6 +41,7 @@ #include #include #include +#include #include #include @@ -130,14 +131,52 @@ void release_fiq(struct fiq_handler *f) static int fiq_start; +/* These hacks use backdoors into the interrupt controller to perform FIQ/IRQ + * routing. These hacks are nasty and completely incompatible with (working) + * multiarch kernels. Additionally these hacks don't count enable/disable + * properly... + * + * This should probably all be replaced with virtual interrupt numbers + * that the intc already knows to bind to FIQ. + */ +#ifdef CONFIG_ARCH_VERSATILE +#define USE_VIC_HACK +#else +#define USE_GIC_HACK +#endif + void enable_fiq(int fiq) { +#ifdef USE_VIC_HACK + vic_set_fiq(fiq, true); +#endif +#ifdef USE_GIC_HACK +{ + struct irq_data *irq_data = irq_get_irq_data(fiq); + + extern void gic_set_group_irq(struct irq_data *d, int group); + gic_set_group_irq(irq_data, 0); +} +#endif + enable_irq(fiq + fiq_start); } void disable_fiq(int fiq) { disable_irq(fiq + fiq_start); + +#ifdef USE_VIC_HACK + vic_set_fiq(fiq, false); +#endif +#ifdef USE_GIC_HACK +{ + struct irq_data *irq_data = irq_get_irq_data(fiq); + + extern void gic_set_group_irq(struct irq_data *d, int group); + gic_set_group_irq(irq_data, 1); +} +#endif } void eoi_fiq(int fiq) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index aa8efe4..c25632b 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -173,6 +173,33 @@ static void gic_unmask_irq(struct irq_data *d) raw_spin_unlock(&irq_controller_lock); } +/*static*/ void gic_set_group_irq(struct irq_data *d, int group) +{ + unsigned long flags; + unsigned int reg = gic_irq(d) / 32 * 4; + u32 mask = 1 << (gic_irq(d) % 32); + u32 val; + + raw_spin_lock_irqsave(&irq_controller_lock, flags); + val = readl_relaxed(gic_dist_base(d) + GIC_DIST_IGROUP + reg); + if (group) + val |= mask; + else + val &= ~mask; + writel_relaxed(val, gic_dist_base(d) + GIC_DIST_IGROUP + reg); + raw_spin_unlock_irqrestore(&irq_controller_lock, flags); +} + +/*static*/ int gic_get_group_irq(struct irq_data *d) +{ + unsigned int reg = gic_irq(d) / 32 * 4; + u32 mask = 1 << (gic_irq(d) % 32); + u32 val; + + val = readl_relaxed(gic_dist_base(d) + GIC_DIST_IGROUP + reg); + return !!(val & mask); +} + static void gic_eoi_irq(struct irq_data *d) { if (gic_arch_extn.irq_eoi) {