From patchwork Mon Dec 23 18:10:32 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taras Kondratiuk X-Patchwork-Id: 22737 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pa0-f72.google.com (mail-pa0-f72.google.com [209.85.220.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 26A6120555 for ; Mon, 23 Dec 2013 18:10:53 +0000 (UTC) Received: by mail-pa0-f72.google.com with SMTP id rd3sf16188866pab.7 for ; Mon, 23 Dec 2013 10:10:52 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=EWbZ+wqHUUsDsUMX32ohfdbo2N7DG08mR1CDo1DAl3k=; b=knKDqhHYPg7TrBR9DjOOj9Oqm+jPlN37j8ON97sscUtv7/u8ecXgz3/OhWkJxao8Mr OM81ehzv63XB9HbZ5p42jHdN8DrYoXLf5LNxw3TFMjOS6wAjQ8cw0+OV55OSPVKDp28V jhYoqIa/QzyWi2iTtvM78tgPVyD904WC/zMUEQzh7EqtSLeeYISS7KHVxPWwBxjSXOPr sLLq3gp8yW1lBxoXeCBEUUhcQtCLTE6o3C+36EFSLrwlyesmfG/k9p1q9jRr8uekQDOd cXtVBLgEVuDgL1uUNpnu0KbVKyBIdon40rbrUm3hTS20Uxp/W0wClckon6EkuU69lEvl NPXg== X-Gm-Message-State: ALoCoQlhwn66VOapIfk76dudxVohXcV3xhWWMTj1Q9Tg4/0uoEP+DElKNGfuJlIqvStZq1psUTR9 X-Received: by 10.66.250.200 with SMTP id ze8mr10446840pac.29.1387822252425; Mon, 23 Dec 2013 10:10:52 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.27.33 with SMTP id q1ls1698906qeg.80.gmail; Mon, 23 Dec 2013 10:10:52 -0800 (PST) X-Received: by 10.53.1.231 with SMTP id bj7mr284971vdd.55.1387822252303; Mon, 23 Dec 2013 10:10:52 -0800 (PST) Received: from mail-ve0-f176.google.com (mail-ve0-f176.google.com [209.85.128.176]) by mx.google.com with ESMTPS id k2si271414vcf.71.2013.12.23.10.10.52 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 23 Dec 2013 10:10:52 -0800 (PST) Received-SPF: neutral (google.com: 209.85.128.176 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.176; Received: by mail-ve0-f176.google.com with SMTP id oz11so2958157veb.7 for ; Mon, 23 Dec 2013 10:10:52 -0800 (PST) X-Received: by 10.220.53.135 with SMTP id m7mr14531969vcg.12.1387822251996; Mon, 23 Dec 2013 10:10:51 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.59.13.131 with SMTP id ey3csp245147ved; Mon, 23 Dec 2013 10:10:51 -0800 (PST) X-Received: by 10.14.150.5 with SMTP id y5mr4085722eej.73.1387822250999; Mon, 23 Dec 2013 10:10:50 -0800 (PST) Received: from mail-ea0-f173.google.com (mail-ea0-f173.google.com [209.85.215.173]) by mx.google.com with ESMTPS id e2si21248201eeg.114.2013.12.23.10.10.50 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 23 Dec 2013 10:10:50 -0800 (PST) Received-SPF: neutral (google.com: 209.85.215.173 is neither permitted nor denied by best guess record for domain of taras.kondratiuk@linaro.org) client-ip=209.85.215.173; Received: by mail-ea0-f173.google.com with SMTP id o10so2490838eaj.32 for ; Mon, 23 Dec 2013 10:10:50 -0800 (PST) X-Received: by 10.14.88.5 with SMTP id z5mr829680eee.101.1387822250362; Mon, 23 Dec 2013 10:10:50 -0800 (PST) Received: from condor-x220.synapse.com ([195.238.93.36]) by mx.google.com with ESMTPSA id o47sm47754698eem.21.2013.12.23.10.10.49 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 23 Dec 2013 10:10:50 -0800 (PST) From: Taras Kondratiuk To: Tony Lindgren Cc: patches@linaro.org, linaro-networking@linaro.org, linaro-kernel@lists.linaro.org, Victor Kamensky , Taras Kondratiuk , Russell King , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/4] ARM: OMAP: dmtimer: raw read and write endian fix Date: Mon, 23 Dec 2013 20:10:32 +0200 Message-Id: <1387822234-11167-3-git-send-email-taras.kondratiuk@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1387822234-11167-1-git-send-email-taras.kondratiuk@linaro.org> References: <1387822234-11167-1-git-send-email-taras.kondratiuk@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: taras.kondratiuk@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.176 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Victor Kamensky All OMAP IP blocks expect LE data, but CPU may operate in BE mode. Need to use endian neutral functions to read/write h/w registers. I.e instead of __raw_read[lw] and __raw_write[lw] functions code need to use read[lw]_relaxed and write[lw]_relaxed functions. If the first simply reads/writes register, the second will byteswap it if host operates in BE mode. Changes are trivial sed like replacement of __raw_xxx functions with xxx_relaxed variant. Signed-off-by: Victor Kamensky Signed-off-by: Taras Kondratiuk --- arch/arm/plat-omap/dmtimer.c | 8 ++++---- arch/arm/plat-omap/include/plat/dmtimer.h | 16 ++++++++-------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 869254c..db10169 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -103,7 +103,7 @@ static void omap_timer_restore_context(struct omap_dm_timer *timer) timer->context.tmar); omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, timer->context.tsicr); - __raw_writel(timer->context.tier, timer->irq_ena); + writel_relaxed(timer->context.tier, timer->irq_ena); omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, timer->context.tclr); } @@ -699,9 +699,9 @@ int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask) omap_dm_timer_enable(timer); if (timer->revision == 1) - l = __raw_readl(timer->irq_ena) & ~mask; + l = readl_relaxed(timer->irq_ena) & ~mask; - __raw_writel(l, timer->irq_dis); + writel_relaxed(l, timer->irq_dis); l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l); @@ -722,7 +722,7 @@ unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) return 0; } - l = __raw_readl(timer->irq_stat); + l = readl_relaxed(timer->irq_stat); return l; } diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 2861b15..dd79f30 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -280,20 +280,20 @@ static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg, int posted) { if (posted) - while (__raw_readl(timer->pend) & (reg >> WPSHIFT)) + while (readl_relaxed(timer->pend) & (reg >> WPSHIFT)) cpu_relax(); - return __raw_readl(timer->func_base + (reg & 0xff)); + return readl_relaxed(timer->func_base + (reg & 0xff)); } static inline void __omap_dm_timer_write(struct omap_dm_timer *timer, u32 reg, u32 val, int posted) { if (posted) - while (__raw_readl(timer->pend) & (reg >> WPSHIFT)) + while (readl_relaxed(timer->pend) & (reg >> WPSHIFT)) cpu_relax(); - __raw_writel(val, timer->func_base + (reg & 0xff)); + writel_relaxed(val, timer->func_base + (reg & 0xff)); } static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer) @@ -301,7 +301,7 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer) u32 tidr; /* Assume v1 ip if bits [31:16] are zero */ - tidr = __raw_readl(timer->io_base); + tidr = readl_relaxed(timer->io_base); if (!(tidr >> 16)) { timer->revision = 1; timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET; @@ -385,7 +385,7 @@ static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer, } /* Ack possibly pending interrupt */ - __raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat); + writel_relaxed(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat); } static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer, @@ -399,7 +399,7 @@ static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer, static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer, unsigned int value) { - __raw_writel(value, timer->irq_ena); + writel_relaxed(value, timer->irq_ena); __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0); } @@ -412,7 +412,7 @@ __omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted) static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) { - __raw_writel(value, timer->irq_stat); + writel_relaxed(value, timer->irq_stat); } #endif /* __ASM_ARCH_DMTIMER_H */