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([2804:1b3:a7c1:e3c5:c9b5:f382:64ea:c32b]) by smtp.gmail.com with ESMTPSA id e4-20020aa79804000000b006ecc858b67fsm21705144pfl.175.2024.04.30.05.40.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Apr 2024 05:40:15 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org Cc: Manjunath S Matti , Peter Bergner Subject: [PATCH] powerpc: Fix __fesetround_inline_nocheck on POWER9+ (BZ 31682) Date: Tue, 30 Apr 2024 09:40:06 -0300 Message-ID: <20240430124011.12408-1-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patch=linaro.org@sourceware.org The e68b1151f7460d5fa88c3a567c13f66052da79a7 commit changed the __fesetround_inline_nocheck implementation to use mffscrni (through __fe_mffscrn) instead of mtfsfi. For generic powerpc ceil/floor/trunc, the function is supposed to not change the Floating-Point Inexact Exception Enable bit, however mffscrni clear bits 56:63 (VE, OE, UE, ZE, XE, NI, RN), different than mtfsfi. This patch fixes by reverting the optimization for the __fesetround_inline_nocheck. Checked on powerpc-linux-gnu. --- sysdeps/powerpc/fpu/fenv_libc.h | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h index f9167056a8..afcf8d2e61 100644 --- a/sysdeps/powerpc/fpu/fenv_libc.h +++ b/sysdeps/powerpc/fpu/fenv_libc.h @@ -182,19 +182,13 @@ __fesetround_inline (int round) return 0; } -/* Same as __fesetround_inline, however without runtime check to use DFP - mtfsfi syntax (as relax_fenv_state) or if round value is valid. */ +/* Same as __fesetround_inline, but it does not change the floating-point + exceptions bits, and without runtime check to use DFP mtfsfi syntax + (as relax_fenv_state), or if round value is valid. */ static inline void __fesetround_inline_nocheck (const int round) { -#ifdef _ARCH_PWR9 - __fe_mffscrn (round); -#else - if (__glibc_likely (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00)) - __fe_mffscrn (round); - else - asm volatile ("mtfsfi 7,%0" : : "n" (round)); -#endif + asm volatile ("mtfsfi 7,%0" : : "n" (round)); } #define FPSCR_MASK(bit) (1 << (31 - (bit)))