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([2804:1b3:a7c0:a715:dd81:f992:f726:338a]) by smtp.gmail.com with ESMTPSA id e15-20020a05620a12cf00b0076eee688a95sm693833qkl.0.2023.11.03.05.24.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 05:24:29 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org, Bruno Haible Subject: [PATCH 4/7] manual: Clarify undefined behavior of feenableexcept (BZ 31019) Date: Fri, 3 Nov 2023 09:24:13 -0300 Message-Id: <20231103122416.2724355-5-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231103122416.2724355-1-adhemerval.zanella@linaro.org> References: <20231103122416.2724355-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patch=linaro.org@sourceware.org From: Bruno Haible * manual/arith.texi (Control Functions): Explain undefined behavior of feenableexcept in a special case. --- manual/arith.texi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/manual/arith.texi b/manual/arith.texi index fa7110e992..68c6446a5b 100644 --- a/manual/arith.texi +++ b/manual/arith.texi @@ -1176,6 +1176,12 @@ enabled, the status of the other exceptions is not changed. The function returns the previous enabled exceptions in case the operation was successful, @code{-1} otherwise. + +Note: Enabling traps for an exception for which the exception flag is +currently already set (@pxref{Status bit operations}) has undefined +consequences: it may or may not trigger a trap immediately. +@c It triggers a trap immediately on powerpc*, at the next floating- +@c instruction on i386, and not at all on the other CPUs. @end deftypefun @deftypefun int fedisableexcept (int @var{excepts})