From patchwork Mon Oct 23 21:36:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Adhemerval Zanella Netto X-Patchwork-Id: 737305 Delivered-To: patch@linaro.org Received: by 2002:adf:dd81:0:b0:32d:baff:b0ca with SMTP id x1csp1735659wrl; Mon, 23 Oct 2023 14:37:43 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFarvuYTsJPBcikTqBCjeoylSJotWTQxJHDRmIiDvQ3TXa1E/63jSTq12DDiRzGDF1yN+vQ X-Received: by 2002:a05:622a:118e:b0:41c:bbf3:b24b with SMTP id m14-20020a05622a118e00b0041cbbf3b24bmr12349217qtk.27.1698097062812; Mon, 23 Oct 2023 14:37:42 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1698097062; cv=pass; d=google.com; s=arc-20160816; b=pCGbL/HGx9O7nNhRrxh/9ouw4StvrSiX6aBZP3DZD2WFLJMFD+QP+2DOQLllYRIXqv 7CPNOrmfOC/wcyXFtemxvrgRSm4D42BM4ywOfnJiJBMtzMTDlGtTr/VEsdtUvvs48JEo /IvCcsSPVODF4M1T9E6w51iVi+oQtlSKmdP61YoXRXp3n6ohgdCIaQ/myEB//Pwik1hS 3qtiBgtnO9dILpidpf/jSm8LKy3VmMKyyhn8nosK6pPIW1zIJ33HukOx8/X6BwWFFW4n NX/8gamJDHxs5/CeQxGmZeB9tKmbRqR8umrN5IoOSDlG280hq2TCLgVBT01BwJ7z8D5w F5QQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=fVL3fJeVFgDyC8rls6M1r3FJNHubHp4CEVWJzTH5jeQ=; fh=Rk9vnpDApgYog/EhmGDFyutcQpHXbdLZmc0l8HNU7lw=; b=vC0mVbG6TmLcREfV58X9lT+8bvaUunwHd02uGuVTTYwElNKaIZfSuYXI+ywsQIKLxm w5zsCPQsyf3YdVvpiy/7EwmqV5ZC3IOXvaXcQLFHmAKKq/bCSd+U+JPRpQNqEQhGFeoC iPVBLGyvS+1vMirI2e5jWuyxIOMzR+FDrVauglwUI4lXa7AHXE8B95c76QIKAQ40ZkYc hbaNmioIqYG90QjrPU8Nqsih3SDzAxwjHeBlOgJ0VGYLrE3dJYtMWRBqFx2wJ18bJqLm FX1GXpE8NN/DQqHvGcbUGbzQ5pqgzEsF4Odx4LDyAdcrgXKoUchPSZ98dO+6cg8cUdbr Zihw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=v8+D0nwn; arc=pass (i=1); spf=pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="libc-alpha-bounces+patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id w6-20020ac857c6000000b0041971a2b466si5967902qta.715.2023.10.23.14.37.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 14:37:42 -0700 (PDT) Received-SPF: pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=v8+D0nwn; arc=pass (i=1); spf=pass (google.com: domain of libc-alpha-bounces+patch=linaro.org@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="libc-alpha-bounces+patch=linaro.org@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 78C0B3857B93 for ; Mon, 23 Oct 2023 21:37:42 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by sourceware.org (Postfix) with ESMTPS id D10263857009 for ; Mon, 23 Oct 2023 21:37:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D10263857009 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linaro.org ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D10263857009 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2607:f8b0:4864:20::436 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698097034; cv=none; b=QBiAg+Z8OSDMPjvL++v0fd5EYx4TLRkK7EmWEGDTKzVfv5EMsR245x6YrqL+zFbG1uf96du5CCbotipQjJ2Q30g92Niqj5W62J3XGmjvgrYK/A3n/6hv8ZHR0B7s56Qc9+Ted/EZP9FQyERlov0nPFvkyGK7i3tatX0JBey5AuI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698097034; c=relaxed/simple; bh=mzOfBSSLNJoBa8H8yXePyTj4wP8ZGeTsQXSgokPD+hw=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=dyaZx7vm66/A1qbNIUc+tDxsYeiPB2djR34EbyBTMStHqhAXhSA7kZzmTJsZU+MwDVYjRZvbP8o1vBVDJ6hpHapl684ERW7blXr7aiyEWAJGXSSrDGMaPhbPKTid0HwB/y90ztV4au1xpvdovCO7ku2b1amB1+WzBgv/rAz1Cx4= ARC-Authentication-Results: i=1; server2.sourceware.org Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-6b709048d8eso2905367b3a.2 for ; Mon, 23 Oct 2023 14:37:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698097031; x=1698701831; darn=sourceware.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fVL3fJeVFgDyC8rls6M1r3FJNHubHp4CEVWJzTH5jeQ=; b=v8+D0nwnQTNt4WPppzNzL2OPk7iHKTzhvwmyq14lmXF0xOEQmgpVpElgugQtON6rC4 Dp998E1BvbJEtz7y6Tewmk6iNDCOkGHY76HbYN46EpGiFZlgBJKpsJp+6i0TG9nvThJo Oc1R6d3A01lQ5nJrBcHpim2r4GUmMklF5bGr35Iapd/tHjO+zuH+1zkcI0IQahDzeI99 rDJuX3nB7giXIs7igiSA6DSr8eBtqalm/orDN1kEwiBjNPxLt2g0uG7jfk0CYSlnibSY uE6BAUlBLRdmjMsHjMQqqJZ4ieWF1H7c8VN2nk+4JQ+nyj6CXPbwvJGFbVBG3vlCTElC /eLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698097031; x=1698701831; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fVL3fJeVFgDyC8rls6M1r3FJNHubHp4CEVWJzTH5jeQ=; b=WLDbPomBGwhRORnyHngnqYFaHOIN8xqgwbJvHpgqclj42bU78Vh75Av+Bpn6HGdQ7v SaOBpcvgxUYyYUKXPhhu1ADZvUuN23yjbEsCIsdMwjw/xmxjEJFL9hIbIVM79ytK/8sF T5vCtOcIyTu/8LrCJ5tSEMnTpQ4YpVQ85XWweMzvC49UW6AbcCzGvmiLz6fh4CNWYVSz 4k4WNzOGX9ITFcXNQ3C5H0y9iHdOzc3wpzoI3qHyXoTTao2dWz8u8VCrFetj7804dfg/ g6jruMSsn6sQD0PPSpWPIAKp9wIMYjKu62sm0kp1cJryYtVhOnz653fE/HCBanqmJZs6 u8/Q== X-Gm-Message-State: AOJu0YxIXmJQc4atRSrS2eQIpRR36FbzQ/3BbVZBOEVPe5CZLwWF5CK8 8E+FXY2xncfWYxaIgARtOpUSGoxkARRDqxfJ4LD1hg== X-Received: by 2002:a05:6a00:1953:b0:6be:b7c:f703 with SMTP id s19-20020a056a00195300b006be0b7cf703mr8560800pfk.5.1698097031234; Mon, 23 Oct 2023 14:37:11 -0700 (PDT) Received: from mandiga.. ([2804:1b3:a7c3:a647:232:4b54:1e33:3494]) by smtp.gmail.com with ESMTPSA id fe12-20020a056a002f0c00b0066a4e561beesm6819443pfb.173.2023.10.23.14.37.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Oct 2023 14:37:10 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org Cc: Bruno Haible Subject: [PATCH 3/3] x86: Do not raises floating-point exception traps on fesetexceptflag (BZ 30990) Date: Mon, 23 Oct 2023 18:36:59 -0300 Message-Id: <20231023213659.3236496-4-adhemerval.zanella@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023213659.3236496-1-adhemerval.zanella@linaro.org> References: <20231023213659.3236496-1-adhemerval.zanella@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patch=linaro.org@sourceware.org From: Bruno Haible According to ISO C23 (7.6.4.5), fesetexceptflag is supposed to set floating-point exception flags without raising a trap. The flags can be set in the 387 unit or in the SSE unit. When we need to clear a flag, we need to do so in both units, due to the way fetestexcept is implemented. When we need to set a flag, it is sufficient to do it in the SSE unit, because that is guaranteed to not trap. However, on i386 CPUs that have only a 387 unit, set the flags in the 387, as long as this cannot trap. Co-authored-by: Adhemerval Zanella --- math/test-fexcept-traps.c | 11 ++++++ sysdeps/i386/fpu/fsetexcptflg.c | 58 ++++++++++++++++++++----------- sysdeps/x86_64/fpu/fsetexcptflg.c | 24 +++++++------ 3 files changed, 62 insertions(+), 31 deletions(-) diff --git a/math/test-fexcept-traps.c b/math/test-fexcept-traps.c index 9b8f583ae6..a486d17951 100644 --- a/math/test-fexcept-traps.c +++ b/math/test-fexcept-traps.c @@ -19,6 +19,7 @@ #include #include #include +#include static int do_test (void) @@ -67,6 +68,16 @@ do_test (void) where setting the exception might result in traps the function should return a nonzero value. */ ret = fesetexceptflag (&saved, FE_ALL_EXCEPT); + + /* Execute some floating-point operations, since on some CPUs exceptions + triggers a trap only at the next floating-point instruction. */ + double a = 1.0; + double b = a + a; + math_force_eval (b); + long double al = 1.0L; + long double bl = al + al; + math_force_eval (bl); + if (ret != 0 && !EXCEPTION_SET_FORCES_TRAP) { puts ("fesetexceptflag failed"); diff --git a/sysdeps/i386/fpu/fsetexcptflg.c b/sysdeps/i386/fpu/fsetexcptflg.c index e724b7d6fd..ccbcf35e8e 100644 --- a/sysdeps/i386/fpu/fsetexcptflg.c +++ b/sysdeps/i386/fpu/fsetexcptflg.c @@ -17,42 +17,58 @@ . */ #include -#include -#include #include -#include int __fesetexceptflag (const fexcept_t *flagp, int excepts) { - fenv_t temp; + /* The flags can be set in the 387 unit or in the SSE unit. When we need to + clear a flag, we need to do so in both units, due to the way fetestexcept + is implemented. + When we need to set a flag, it is sufficient to do it in the SSE unit, + because that is guaranteed to not trap. However, on i386 CPUs that have + only a 387 unit, set the flags in the 387, as long as this cannot trap. */ - /* Get the current environment. We have to do this since we cannot - separately set the status word. */ - __asm__ ("fnstenv %0" : "=m" (*&temp)); + fenv_t temp; - temp.__status_word &= ~(excepts & FE_ALL_EXCEPT); - temp.__status_word |= *flagp & excepts & FE_ALL_EXCEPT; + excepts &= FE_ALL_EXCEPT; - /* Store the new status word (along with the rest of the environment. - Possibly new exceptions are set but they won't get executed unless - the next floating-point instruction. */ - __asm__ ("fldenv %0" : : "m" (*&temp)); + /* Get the current x87 FPU environment. We have to do this since we + cannot separately set the status word. */ + __asm__ ("fnstenv %0" : "=m" (*&temp)); - /* If the CPU supports SSE, we set the MXCSR as well. */ if (CPU_FEATURE_USABLE (SSE)) { - unsigned int xnew_exc; + unsigned int mxcsr; + + /* Clear relevant flags. */ + temp.__status_word &= ~(excepts & ~ *flagp); - /* Get the current MXCSR. */ - __asm__ ("stmxcsr %0" : "=m" (*&xnew_exc)); + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); - /* Set the relevant bits. */ - xnew_exc &= ~(excepts & FE_ALL_EXCEPT); - xnew_exc |= *flagp & excepts & FE_ALL_EXCEPT; + /* And now similarly for SSE. */ + __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); + + /* Clear or set relevant flags. */ + mxcsr ^= (mxcsr ^ *flagp) & excepts; /* Put the new data in effect. */ - __asm__ ("ldmxcsr %0" : : "m" (*&xnew_exc)); + __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); + } + else + { + /* Clear or set relevant flags. */ + temp.__status_word ^= (temp.__status_word ^ *flagp) & excepts; + + if ((~temp.__control_word) & temp.__status_word & excepts) + /* Setting the exception flags may trigger a trap (at the next + floating-point instruction, but that does not matter). + ISO C 23 ยง 7.6.4.5 does not allow it. */ + return -1; + + /* Store the new status word (along with the rest of the environment). */ + __asm__ ("fldenv %0" : : "m" (*&temp)); } /* Success. */ diff --git a/sysdeps/x86_64/fpu/fsetexcptflg.c b/sysdeps/x86_64/fpu/fsetexcptflg.c index a3ac1dea01..2ce2b509f2 100644 --- a/sysdeps/x86_64/fpu/fsetexcptflg.c +++ b/sysdeps/x86_64/fpu/fsetexcptflg.c @@ -22,30 +22,34 @@ int fesetexceptflag (const fexcept_t *flagp, int excepts) { + /* The flags can be set in the 387 unit or in the SSE unit. + When we need to clear a flag, we need to do so in both units, + due to the way fetestexcept() is implemented. + When we need to set a flag, it is sufficient to do it in the SSE unit, + because that is guaranteed to not trap. */ + fenv_t temp; unsigned int mxcsr; - /* XXX: Do we really need to set both the exception in both units? - Shouldn't it be enough to set only the SSE unit? */ + excepts &= FE_ALL_EXCEPT; /* Get the current x87 FPU environment. We have to do this since we cannot separately set the status word. */ __asm__ ("fnstenv %0" : "=m" (*&temp)); - temp.__status_word &= ~(excepts & FE_ALL_EXCEPT); - temp.__status_word |= *flagp & excepts & FE_ALL_EXCEPT; + /* Clear relevant flags. */ + temp.__status_word &= ~(excepts & ~ *flagp); - /* Store the new status word (along with the rest of the environment. - Possibly new exceptions are set but they won't get executed unless - the next floating-point instruction. */ + /* Store the new status word (along with the rest of the environment). */ __asm__ ("fldenv %0" : : "m" (*&temp)); - /* And now the same for SSE. */ + /* And now similarly for SSE. */ __asm__ ("stmxcsr %0" : "=m" (*&mxcsr)); - mxcsr &= ~(excepts & FE_ALL_EXCEPT); - mxcsr |= *flagp & excepts & FE_ALL_EXCEPT; + /* Clear or set relevant flags. */ + mxcsr ^= (mxcsr ^ *flagp) & excepts; + /* Put the new data in effect. */ __asm__ ("ldmxcsr %0" : : "m" (*&mxcsr)); /* Success. */