From patchwork Tue Nov 8 01:06:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Miller X-Patchwork-Id: 81214 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp1300645qge; Mon, 7 Nov 2016 17:06:45 -0800 (PST) X-Received: by 10.98.105.68 with SMTP id e65mr18260716pfc.174.1478567205710; Mon, 07 Nov 2016 17:06:45 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id sj7si28219752pac.5.2016.11.07.17.06.45 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 07 Nov 2016 17:06:45 -0800 (PST) Received-SPF: pass (google.com: domain of libc-alpha-return-74509-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org; spf=pass (google.com: domain of libc-alpha-return-74509-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=libc-alpha-return-74509-patch=linaro.org@sourceware.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:date:message-id:to:cc:subject:from:in-reply-to :references:mime-version:content-type:content-transfer-encoding; q=dns; s=default; b=dbx2qdpr5mJD0A2KaAYkChYJ3vDxCB7gIS3/dJLeAi2 tkRdVQ7YInTzIAYjB6ApUk6WKE0pwx4czYY0Km4OTPPafRcuFa+km27MuHJaGxsh MYXqhdaMy3MUhhPyNWOQN9lbDUHB+nm3m295xK+8VamMIisiMIX2mEY1Fc7YT+4c = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:date:message-id:to:cc:subject:from:in-reply-to :references:mime-version:content-type:content-transfer-encoding; s=default; bh=dzGrJWdUcGqSZtpEMh3M7r2BpHM=; b=BWl7nLhfWlvgKbLcy TPBI/LZ68hIIf9Ed5hOJWFDUWMk6ZIMo6NYmdDxjskzxiJvIxb8t/C0kF85VEPq6 y2RYsy3Sr2C1VTqfLu9i2bsBrGuQHEh51JjgzJmrKtV/gRfXhI04+HKQ3a+QkL5b TXbKntri0gPDNhMXr2d/gQvb+k= Received: (qmail 105281 invoked by alias); 8 Nov 2016 01:06:34 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 105267 invoked by uid 89); 8 Nov 2016 01:06:33 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=3.5 required=5.0 tests=AWL, BAYES_95, KAM_LAZY_DOMAIN_SECURITY autolearn=no version=3.3.2 spammy=Sam, H*c:Multipart, casa, firstly X-HELO: shards.monkeyblade.net Date: Mon, 07 Nov 2016 20:06:18 -0500 (EST) Message-Id: <20161107.200618.307872104473677470.davem@davemloft.net> To: sam@ravnborg.org Cc: carlos@redhat.com, triegel@redhat.com, adhemerval.zanella@linaro.org, andreas@gaisler.com, libc-alpha@sourceware.org, software@gaisler.com Subject: Re: Remove sparcv8 support From: David Miller In-Reply-To: <20161107212050.GA27481@ravnborg.org> References: <502720f6-3057-41f5-7832-4b219f5f729f@redhat.com> <20161107.113825.631166023186879199.davem@davemloft.net> <20161107212050.GA27481@ravnborg.org> Mime-Version: 1.0 From: Sam Ravnborg Date: Mon, 7 Nov 2016 22:20:50 +0100 > casemul.S is missing. > So all the fun kernel stuf was not included in the patch... Ugh, someone asked me about this but asked me privately so I only sent the corrected patch to them privately :-/ Here it is: >From acdd40e01a98e2c4bf477d5d66c183716e7562c5 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Mon, 7 Nov 2016 08:27:05 -0800 Subject: [PATCH] sparc64: Add CAS emulation trap. Older 32-bit sparc cpus (other than LEON) lack a CAS instruction, so we need to provide some kind of helper infrastructure in the kernel to emulate it. This is the first part which firstly defines the basic infrastructure and the simplest implementation, which is to just directly execute the instruction on sparc64. We make use of the window fill/spill fault unwind facilities to make this as simple as possible. When we take a full TSB miss, we check if the trap level is greater than one, and if so unwind the trap to one of the final 3 instructions of the interrupted trap handler's block. Which of the three to use is based upon whether this is a real fault, an unaligned access, or a data access exception (ie. bus error). Signed-off-by: David S. Miller --- arch/sparc/include/uapi/asm/unistd.h | 1 + arch/sparc/kernel/Makefile | 1 + arch/sparc/kernel/casemul.S | 66 ++++++++++++++++++++++++++++++++++++ arch/sparc/kernel/sys_sparc_64.c | 2 +- arch/sparc/kernel/ttable_64.S | 3 +- 5 files changed, 71 insertions(+), 2 deletions(-) create mode 100644 arch/sparc/kernel/casemul.S diff --git a/arch/sparc/include/uapi/asm/unistd.h b/arch/sparc/include/uapi/asm/unistd.h index 36eee81..0725911 100644 --- a/arch/sparc/include/uapi/asm/unistd.h +++ b/arch/sparc/include/uapi/asm/unistd.h @@ -430,6 +430,7 @@ /* Bitmask values returned from kern_features system call. */ #define KERN_FEATURE_MIXED_MODE_STACK 0x00000001 +#define KERN_FEATURE_CAS_EMUL 0x00000002 #ifdef __32bit_syscall_numbers__ /* Sparc 32-bit only has the "setresuid32", "getresuid32" variants, diff --git a/arch/sparc/kernel/Makefile b/arch/sparc/kernel/Makefile index fa3c02d..1166638 100644 --- a/arch/sparc/kernel/Makefile +++ b/arch/sparc/kernel/Makefile @@ -21,6 +21,7 @@ CFLAGS_REMOVE_perf_event.o := -pg CFLAGS_REMOVE_pcr.o := -pg endif +obj-$(CONFIG_SPARC64) += casemul.o obj-$(CONFIG_SPARC64) += urtt_fill.o obj-$(CONFIG_SPARC32) += entry.o wof.o wuf.o obj-$(CONFIG_SPARC32) += etrap_32.o diff --git a/arch/sparc/kernel/casemul.S b/arch/sparc/kernel/casemul.S new file mode 100644 index 0000000..237221f --- /dev/null +++ b/arch/sparc/kernel/casemul.S @@ -0,0 +1,66 @@ +#include +#include +#include +#include +#include + + .text + .align 128 + .globl emulate_cas + .type emulate_cas,#function +emulate_cas: + casa [%o0] ASI_AIUP, %o1, %o2 + done + nop; nop; nop; nop; nop; nop; + nop; nop; nop; nop; nop; nop; nop; nop + nop; nop; nop; nop; nop; nop; nop; nop + nop; nop; nop; nop; nop; + ba,a,pt %xcc, 3f + ba,a,pt %xcc, 2f + ba,a,pt %xcc, 1f + .size emulate_cas,.-emulate_cas + + /* Fault */ +1: TRAP_LOAD_THREAD_REG(%g6, %g1) + stb %g4, [%g6 + TI_FAULT_CODE] + stx %g5, [%g6 + TI_FAULT_ADDR] + ba,pt %xcc, etrap + rd %pc, %g7 + call do_sparc64_fault + add %sp, PTREGS_OFF, %o0 + ba,a,pt %xcc, rtrap + + /* Memory address unaligned */ +2: ba,pt %xcc, etrap + rd %pc, %g7 + sethi %hi(tlb_type), %g1 + lduw [%g1 + %lo(tlb_type)], %g1 + cmp %g1, 3 + bne,pt %icc, 1f + add %sp, PTREGS_OFF, %o0 + mov %l4, %o2 + call sun4v_do_mna + mov %l5, %o1 + ba,a,pt %xcc, rtrap +1: mov %l4, %o1 + mov %l5, %o2 + call mem_address_unaligned + nop + ba,a,pt %xcc, rtrap + + /* Data access exception */ +3: ba,pt %xcc, etrap + rd %pc, %g7 + sethi %hi(tlb_type), %g1 + mov %l4, %o1 + lduw [%g1 + %lo(tlb_type)], %g1 + mov %l5, %o2 + cmp %g1, 3 + bne,pt %icc, 1f + add %sp, PTREGS_OFF, %o0 + call sun4v_data_access_exception + nop + ba,a,pt %xcc, rtrap +1: call spitfire_data_access_exception + nop + ba,a,pt %xcc, rtrap diff --git a/arch/sparc/kernel/sys_sparc_64.c b/arch/sparc/kernel/sys_sparc_64.c index fe8b8ee..d55e8b8 100644 --- a/arch/sparc/kernel/sys_sparc_64.c +++ b/arch/sparc/kernel/sys_sparc_64.c @@ -643,5 +643,5 @@ SYSCALL_DEFINE5(rt_sigaction, int, sig, const struct sigaction __user *, act, asmlinkage long sys_kern_features(void) { - return KERN_FEATURE_MIXED_MODE_STACK; + return KERN_FEATURE_MIXED_MODE_STACK | KERN_FEATURE_CAS_EMUL; } diff --git a/arch/sparc/kernel/ttable_64.S b/arch/sparc/kernel/ttable_64.S index c6dfdaa..3364019 100644 --- a/arch/sparc/kernel/ttable_64.S +++ b/arch/sparc/kernel/ttable_64.S @@ -147,7 +147,8 @@ tl0_resv11e: TRAP_UTRAP(UT_TRAP_INSTRUCTION_30,0x11e) TRAP_UTRAP(UT_TRAP_INSTRUC tl0_getcc: GETCC_TRAP tl0_setcc: SETCC_TRAP tl0_getpsr: TRAP(do_getpsr) -tl0_resv123: BTRAP(0x123) BTRAP(0x124) BTRAP(0x125) BTRAP(0x126) BTRAP(0x127) +tl0_cas: TRAP_NOSAVE(emulate_cas) +tl0_resv124: BTRAP(0x124) BTRAP(0x125) BTRAP(0x126) BTRAP(0x127) tl0_resv128: BTRAP(0x128) BTRAP(0x129) BTRAP(0x12a) BTRAP(0x12b) BTRAP(0x12c) tl0_resv12d: BTRAP(0x12d) BTRAP(0x12e) BTRAP(0x12f) BTRAP(0x130) BTRAP(0x131) tl0_resv132: BTRAP(0x132) BTRAP(0x133) BTRAP(0x134) BTRAP(0x135) BTRAP(0x136) -- 2.1.2.532.g19b5d50