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[209.132.180.131]) by mx.google.com with ESMTPS id b25si1266269pgn.747.2018.04.11.14.17.06 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Apr 2018 14:17:07 -0700 (PDT) Received-SPF: pass (google.com: domain of libc-alpha-return-91506-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=amqSO+Ta; spf=pass (google.com: domain of libc-alpha-return-91506-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=libc-alpha-return-91506-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id:in-reply-to :references; q=dns; s=default; b=rg0zjyjgoJyupR2VQKd43aK5MMh9mp3 V2109N4XGFfFuuUvdSGhm4kIAlIt5UVmtEtc60r9m423JB1Qytq+oiBP862u6YfX bOILNa66oDgDp66uIhIdlqq5mAXAEF3AtfAF63jhfEOPy2RcRE/Q+5MSPb5aCP3t z+DBhNU/ihI8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id:in-reply-to :references; s=default; bh=Awc7b/g3vhNH/IkAxAhZNCLfsME=; b=amqSO +TaE987CL8a8j4AcQgUDU8MNKwQeP6rP0x0LzQJnSIMIXB1H7/ocjL+A83Xjk8qx S1gwYx8xxPNfwV4lOEFjvkIyGqRifv+90WNyyiWbOjjT+HBPiX8ZzGVOM6auFEeN iff8TmJA3wURN+nCu8Wo96PKeH1ekxGtbmh3IQ= Received: (qmail 118343 invoked by alias); 11 Apr 2018 21:16:34 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 118132 invoked by uid 89); 11 Apr 2018 21:16:33 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.1 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-qk0-f172.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=yI4OijDmohPHDdwCQ1qgbCVd3Lt47FrajgQIGVQrgBU=; b=ne39Y/SJ/3GvB1j00qB3rEJK3BEaBgzUpaBFdLQ19BpZ+NHbzR/oBSYL7z015SYl/u ZHcTzTyy8xqySKyORBXEDMUS+qTH0KwE/d9BWAG/lJ28qujTCEJ/53rc6IFSLgTWdbQ3 h48rQXjHdL4EU7l7TgDk5CQkhCVSZjvJg8VanY24vJJhVO1qJkT/Hf566lRQX3GPkNf4 px0QxeLa6SsFKhUGFbCYFZKJHz6bxCZbamfGTdOrYcn3z3BJvUMO8m4HfZ8dCH3RncTO RozFFEKoiffiD76KRJg/E13DU6BwdA1wdsqivhvRh4H/w8egH/v6XcrH3eU7d7ox/bBz 9rQA== X-Gm-Message-State: ALQs6tBztaKpK+E2DyhQ9BrevEZ3AFxnXTUEmTOT1bOedqmfc6LMhf47 BxFYaaTgipYZAR3UpEkNYKSIn3fUJks= X-Received: by 10.55.76.146 with SMTP id z140mr9569816qka.224.1523481389922; Wed, 11 Apr 2018 14:16:29 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org Subject: [PATCH 4/4] arm: Enable ARM mode for armv6 strlen Date: Wed, 11 Apr 2018 18:16:18 -0300 Message-Id: <1523481378-16290-4-git-send-email-adhemerval.zanella@linaro.org> In-Reply-To: <1523481378-16290-1-git-send-email-adhemerval.zanella@linaro.org> References: <1523481378-16290-1-git-send-email-adhemerval.zanella@linaro.org> Current optimized armv6t2 strlen uses the NO_THUMB wrongly to conditionalize thumb instruction usage. The flags is meant to be defined before sysdep.h inclusion and to indicate the assembly requires to build in ARM mode, not to check whether thumb is enable or not. This patch fixes it by using the GCC provided '__thumb__' instead. Checked on arm-linux-gnueabihf (with -marm -march=armv6t2). * sysdeps/arm/armv6t2/strlen.S (NO_THUMB): Check for __thumb__ instead. --- ChangeLog | 3 +++ sysdeps/arm/armv6t2/strlen.S | 6 +++--- 2 files changed, 6 insertions(+), 3 deletions(-) -- 2.7.4 diff --git a/sysdeps/arm/armv6t2/strlen.S b/sysdeps/arm/armv6t2/strlen.S index 6988183..f4111c3 100644 --- a/sysdeps/arm/armv6t2/strlen.S +++ b/sysdeps/arm/armv6t2/strlen.S @@ -21,7 +21,7 @@ */ -#include /* This might #define NO_THUMB. */ +#include #include #ifdef __ARMEB__ @@ -32,7 +32,7 @@ #define S2HI lsl #endif -#ifndef NO_THUMB +#ifdef __thumb__ /* This code is best on Thumb. */ .thumb #else @@ -146,7 +146,7 @@ ENTRY(strlen) tst tmp1, #4 pld [src, #64] S2HI tmp2, const_m1, tmp2 -#ifdef NO_THUMB +#ifndef __thumb__ mvn tmp1, tmp2 orr data1a, data1a, tmp1 itt ne