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[209.132.180.131]) by mx.google.com with ESMTPS id e125si1484071pfe.244.2018.04.11.14.16.57 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Apr 2018 14:16:59 -0700 (PDT) Received-SPF: pass (google.com: domain of libc-alpha-return-91505-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=abtSJvbP; spf=pass (google.com: domain of libc-alpha-return-91505-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=libc-alpha-return-91505-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id:in-reply-to :references; q=dns; s=default; b=UdqmnkTR/bsVc9G7vhHCLTa8E0dl0yU M6hc5b7016kIKFuGBSJQ+oNbB+cYWaMcVe8jAkEzFJgJH7ENUlZnSu/w1U+GGEzE oNxMG6vqzY01V9uIwkNtvFn4ze2mFqdUsClzkQT8Rt9JDneBksixDhfko1HB9ARR 2TedDaY7yMTo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:subject:date:message-id:in-reply-to :references; s=default; bh=CjPeuyPhHdyXDlC7ZQjByzM44tY=; b=abtSJ vbPIMaDZ+/VRZMHJkj1MmCJLhOyiGbgCFKhhHR8YhhMYIFZJWXpPn+Esp1iyeldo 7CDBa+6C1tKY4EE9ys/JUIsRP7vj5t2HCTOSJs25IgqUinO6SNQ+38lz5IwZX2tQ ZTZ5loGRM9+Q2y39SyXewsk/oES4/F18fWBjPQ= Received: (qmail 118082 invoked by alias); 11 Apr 2018 21:16:33 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 117834 invoked by uid 89); 11 Apr 2018 21:16:31 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=eor X-HELO: mail-qt0-f181.google.com X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=0xt6HHZb6s6E+hJnS8iCVYKgwYg2GnlNDvMxd4DGV/0=; b=t/XR0TuCb7hJi1URrqTxiG/GMBfoFysykCv7WtWxM+3TDl9TCE14sY4dHD4a0BgO+S z65CEXhSFEClhBpAlyQK+Xv/Nl9/FMg11SKS37XGTbzzsd5vlrBBGje85wQPN2ViioCd 23f5J8Bgn/iGWO4ScdgPviUdyoPEFYi/N2iX8kxxegt45VcJnjPRzxDQ0uHqLQshGxAo vS7h2tx613Y0awJwKAdwkgNjdSoIUZRhXVhsPPrnBovN1qVZ/hDnnV0T5aFAm37sgmfL 9Zq2MTkdzCo4E0YC6eaHoWJdsviBci+oNayYVa7HexAvFtBYCsIiwz1SOzgTq5WZ7hlm ZtaQ== X-Gm-Message-State: ALQs6tA7fRI+/eis/lJ9vomkoCA7o+HzXp3rbGEZrrR6oyoHS9kyJ8M+ xrFPkxScphSXX2OfC2oYJ8wEqk/YU5Y= X-Received: by 10.200.7.69 with SMTP id k5mr9924846qth.165.1523481388565; Wed, 11 Apr 2018 14:16:28 -0700 (PDT) From: Adhemerval Zanella To: libc-alpha@sourceware.org Subject: [PATCH 3/4] arm: Enable ARM mode for armv6 memchr Date: Wed, 11 Apr 2018 18:16:17 -0300 Message-Id: <1523481378-16290-3-git-send-email-adhemerval.zanella@linaro.org> In-Reply-To: <1523481378-16290-1-git-send-email-adhemerval.zanella@linaro.org> References: <1523481378-16290-1-git-send-email-adhemerval.zanella@linaro.org> Current optimized armv6t2 memchr uses the NO_THUMB wrongly to conditionalize thumb instruction usage. The flags is meant to be defined before sysdep.h inclusion and to indicate the assembly requires to build in ARM mode, not to check whether thumb is enable or not. This patch fixes it by using the GCC provided '__thumb__' instead. Checked on arm-linux-gnueabihf (with -marm -march=armv6t2). * sysdeps/arm/armv6t2/memchr.S (NO_THUMB): Check for __thumb__ instead. --- ChangeLog | 3 +++ sysdeps/arm/armv6t2/memchr.S | 10 +++++----- 2 files changed, 8 insertions(+), 5 deletions(-) -- 2.7.4 diff --git a/sysdeps/arm/armv6t2/memchr.S b/sysdeps/arm/armv6t2/memchr.S index bdd385b..03b7f32 100644 --- a/sysdeps/arm/armv6t2/memchr.S +++ b/sysdeps/arm/armv6t2/memchr.S @@ -42,7 +42,7 @@ .syntax unified .text -#ifdef NO_THUMB +#ifndef __thumb__ .arm #else .thumb @@ -91,7 +91,7 @@ ENTRY(memchr) 15: ldrd r4,r5, [r0],#8 -#ifndef NO_THUMB +#ifdef __thumb__ subs r6, r6, #8 #endif eor r4,r4, r1 @ Get it so that r4,r5 have 00's where the bytes match the target @@ -100,7 +100,7 @@ ENTRY(memchr) sel r4, r3, r7 @ bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION uadd8 r5, r5, r7 @ Parallel add 0xff - sets the GE bits for anything that wasn't 0 sel r5, r4, r7 @ chained....bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION -#ifndef NO_THUMB +#ifdef __thumb__ cbnz r5, 60f #else cmp r5, #0 @@ -120,7 +120,7 @@ ENTRY(memchr) and r2,r2,#7 @ Leave the count remaining as the number after the double words have been done 20: -#ifndef NO_THUMB +#ifdef __thumb__ cbz r2, 40f @ 0 length or hit the end already then not found #else cmp r2, #0 @@ -129,7 +129,7 @@ ENTRY(memchr) 21: @ Post aligned section, or just a short call ldrb r3,[r0],#1 -#ifndef NO_THUMB +#ifdef __thumb__ subs r2,r2,#1 eor r3,r3,r1 @ r3 = 0 if match - doesn't break flags from sub cbz r3, 50f