From patchwork Wed Feb 19 17:25:53 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Newton X-Patchwork-Id: 24964 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pa0-f72.google.com (mail-pa0-f72.google.com [209.85.220.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id D6F7020143 for ; Wed, 19 Feb 2014 17:26:15 +0000 (UTC) Received: by mail-pa0-f72.google.com with SMTP id rd3sf1666217pab.3 for ; Wed, 19 Feb 2014 09:26:15 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:mailing-list :precedence:list-id:list-unsubscribe:list-subscribe:list-archive :list-post:list-help:sender:delivered-to:from:to:subject:date :message-id:x-original-sender:x-original-authentication-results; bh=h21Ixj0dV2jgjnbDIvjsJ3e0yVgA/S0Ip7juRi371QU=; b=G8Yr4Bt7P18JG+VQfYBVxEb5XEqVlFh/PXDOsUjbyXSbR8qmO61a9EdLYnlLqeEeWO KS0PdpDdAPQ4usCpXB8t4mG489PlyUfTTx7rMKKYJuurkMOkVKvnT7AU/wpBOdhyo7J6 V+PX4FaGaG1Bh2zEI86/Dl+rutFY/AXt6lPPeJfgOOPkvWQY1I7O8B1cB4fJSSnR4uyV EwylZdtdOaJymvQjylGnZDqEQvdxxmFGwwWBcOXUpcPbeohE++DSdaEFaTR8Wu36IYcu I03qk1Z+udEuQ7DfVyrr5K7641zrznGjxKPo4noJ4UW4kF1RzkO1C1vmM21vdMIYZlEZ NP3w== X-Gm-Message-State: ALoCoQmLUrWX5c9CvJxD0O0W2DO+TN87ezz62V1lxyOPKbjVy21a32fujnHHfpSdsBKM/MVmlE49 X-Received: by 10.68.197.73 with SMTP id is9mr15821042pbc.0.1392830775076; Wed, 19 Feb 2014 09:26:15 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.34.235 with SMTP id l98ls183142qgl.90.gmail; Wed, 19 Feb 2014 09:26:14 -0800 (PST) X-Received: by 10.220.175.198 with SMTP id bb6mr14051904vcb.31.1392830774926; Wed, 19 Feb 2014 09:26:14 -0800 (PST) Received: from mail-ve0-x235.google.com (mail-ve0-x235.google.com [2607:f8b0:400c:c01::235]) by mx.google.com with ESMTPS id uy8si357165vcb.55.2014.02.19.09.26.14 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 19 Feb 2014 09:26:14 -0800 (PST) Received-SPF: neutral (google.com: 2607:f8b0:400c:c01::235 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=2607:f8b0:400c:c01::235; Received: by mail-ve0-f181.google.com with SMTP id jw12so696011veb.26 for ; Wed, 19 Feb 2014 09:26:14 -0800 (PST) X-Received: by 10.220.98.204 with SMTP id r12mr1214332vcn.48.1392830774836; Wed, 19 Feb 2014 09:26:14 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.174.196 with SMTP id u4csp314947vcz; Wed, 19 Feb 2014 09:26:14 -0800 (PST) X-Received: by 10.66.49.74 with SMTP id s10mr41510502pan.0.1392830773930; Wed, 19 Feb 2014 09:26:13 -0800 (PST) Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id ic5si289432pbb.258.2014.02.19.09.26.13 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Feb 2014 09:26:13 -0800 (PST) Received-SPF: pass (google.com: domain of libc-alpha-return-47462-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 24428 invoked by alias); 19 Feb 2014 17:26:04 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Subscribe: List-Archive: List-Post: , List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 24417 invoked by uid 89); 19 Feb 2014 17:26:03 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wg0-f52.google.com X-Received: by 10.180.218.171 with SMTP id ph11mr2629933wic.7.1392830758225; Wed, 19 Feb 2014 09:25:58 -0800 (PST) From: Will Newton To: libc-alpha@sourceware.org Subject: [PATCH v4] ARM: Add SystemTap probes to longjmp and setjmp. Date: Wed, 19 Feb 2014 17:25:53 +0000 Message-Id: <1392830753-3100-1-git-send-email-will.newton@linaro.org> X-Original-Sender: will.newton@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c01::235 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@sourceware.org X-Google-Group-Id: 836684582541 Now the ARM port implements pointer encryption for jmpbufs, gdb needs a SystemTap probe point in longjmp to determine the target PC of a call to longjmp. This patch implements the probe point in longjmp and a similar probe point in setjmp. In order to have all the appropriate registers available to pass to the probe this reorders the layout of jmpbuf, putting the sp and lr registers at the start rather than the end, allowing them to be read and written sequentially. Tested on armv7, no new failures in the glibc testsuite and confirmed that this fixes the gdb.base/longjmp.exp failures in the gdb testsuite. ChangeLog: 2014-01-27 Will Newton * sysdeps/arm/__longjmp.S: Include stap-probe.h. (__longjmp): Restore sp and lr before restoring callee saved registers. Add longjmp and longjmp_target SystemTap probe point. * sysdeps/arm/bits/setjmp.h (__jmp_buf): Update comment. * sysdeps/arm/include/bits/setjmp.h (__JMP_BUF_SP): Define to zero to match jmpbuf layout. * sysdeps/arm/setjmp.S: Include stap-probe.h. (__sigsetjmp): Save sp and lr before saving callee saved registers. Add setjmp SystemTap probe point. --- sysdeps/arm/__longjmp.S | 61 ++++++++++++++++++++++++--------------- sysdeps/arm/bits/setjmp.h | 5 ++-- sysdeps/arm/include/bits/setjmp.h | 2 +- sysdeps/arm/setjmp.S | 12 ++++++-- 4 files changed, 49 insertions(+), 31 deletions(-) Changes in v4: - Update __jmp_buf comment to match the code diff --git a/sysdeps/arm/__longjmp.S b/sysdeps/arm/__longjmp.S index 27c57a1..08521e5 100644 --- a/sysdeps/arm/__longjmp.S +++ b/sysdeps/arm/__longjmp.S @@ -17,6 +17,7 @@ . */ #include +#include #include #include #include @@ -25,31 +26,35 @@ ENTRY (__longjmp) mov ip, r0 - movs r0, r1 /* get the return value in place */ - it eq - moveq r0, #1 /* can't let setjmp() return zero! */ #ifdef CHECK_SP sfi_breg ip, \ - ldr r4, [\B, #32] /* jmpbuf's sp */ + ldr r4, [\B] /* jmpbuf's sp */ cfi_undefined (r4) #ifdef PTR_DEMANGLE PTR_DEMANGLE (r4, r4, a3, a4) #endif CHECK_SP (r4) #endif - sfi_sp sfi_breg ip, \ - ldmia \B!, JMP_BUF_REGLIST + #ifdef PTR_DEMANGLE ldr a4, [ip], #4 - PTR_DEMANGLE (a4, a4, a3, a2) - mov sp, a4 - ldr a4, [ip], #4 - PTR_DEMANGLE2 (lr, a4, a3) + PTR_DEMANGLE (a4, a4, a3, r4) + cfi_undefined (r4) + ldr r4, [ip], #4 + PTR_DEMANGLE2 (r4, r4, a3) #else - ldr sp, [ip], #4 - ldr lr, [ip], #4 + ldr a4, [ip], #4 + ldr r4, [ip], #4 + cfi_undefined (r4) #endif + /* longjmp probe expects longjmp first argument (4@r0), second + argument (-4@r1), and target address (4@r4), respectively. */ + LIBC_PROBE (longjmp, 3, 4@r0, -4@r1, 4@r4) + mov sp, a4 + mov lr, r4 + sfi_sp sfi_breg ip, \ + ldmia \B!, JMP_BUF_REGLIST cfi_restore (v1) cfi_restore (v2) cfi_restore (v3) @@ -67,27 +72,27 @@ ENTRY (__longjmp) #ifdef NEED_HWCAP # ifdef IS_IN_rtld - ldr a2, 1f + ldr a4, 1f ldr a3, .Lrtld_local_ro -0: add a2, pc, a2 - add a2, a2, a3 - ldr a2, [a2, #RTLD_GLOBAL_RO_DL_HWCAP_OFFSET] +0: add a4, pc, a4 + add a4, a4, a3 + ldr a4, [a4, #RTLD_GLOBAL_RO_DL_HWCAP_OFFSET] # else # ifdef PIC - ldr a2, 1f + ldr a4, 1f ldr a3, .Lrtld_global_ro -0: add a2, pc, a2 - ldr a2, [a2, a3] - ldr a2, [a2, #RTLD_GLOBAL_RO_DL_HWCAP_OFFSET] +0: add a4, pc, a4 + ldr a4, [a4, a3] + ldr a4, [a4, #RTLD_GLOBAL_RO_DL_HWCAP_OFFSET] # else - ldr a2, .Lhwcap - ldr a2, [a2, #0] + ldr a4, .Lhwcap + ldr a4, [a4, #0] # endif # endif #endif #ifdef __SOFTFP__ - tst a2, #HWCAP_ARM_VFP + tst a4, #HWCAP_ARM_VFP beq .Lno_vfp #endif @@ -98,7 +103,7 @@ ENTRY (__longjmp) .Lno_vfp: #ifndef ARM_ASSUME_NO_IWMMXT - tst a2, #HWCAP_ARM_IWMMXT + tst a4, #HWCAP_ARM_IWMMXT beq .Lno_iwmmxt /* Restore the call-preserved iWMMXt registers. */ @@ -118,6 +123,14 @@ ENTRY (__longjmp) .Lno_iwmmxt: #endif + /* longjmp_target probe expects longjmp first argument (4@r0), second + argument (-4@r1), and target address (4@r14), respectively. */ + LIBC_PROBE (longjmp_target, 3, 4@r0, -4@r1, 4@r14) + + movs r0, r1 /* get the return value in place */ + it eq + moveq r0, #1 /* can't let setjmp() return zero! */ + DO_RET(lr) #ifdef NEED_HWCAP diff --git a/sysdeps/arm/bits/setjmp.h b/sysdeps/arm/bits/setjmp.h index 41423b2..a687359 100644 --- a/sysdeps/arm/bits/setjmp.h +++ b/sysdeps/arm/bits/setjmp.h @@ -28,9 +28,8 @@ /* The exact set of registers saved may depend on the particular core in use, as some coprocessor registers may need to be saved. The C Library ABI requires that the buffer be 8-byte aligned, and - recommends that the buffer contain 64 words. The first 27 words - are occupied by v1-v6, sl, fp, sp, pc, and d8-d15. (Note that - d8-15 require 17 words, due to the use of fstmx.) */ + recommends that the buffer contain 64 words. The first 26 words + are occupied by sp, lr, v1-v6, sl, fp, and d8-d15. */ typedef int __jmp_buf[64] __attribute__((__aligned__ (8))); #endif diff --git a/sysdeps/arm/include/bits/setjmp.h b/sysdeps/arm/include/bits/setjmp.h index 220dfe8..5877c1f 100644 --- a/sysdeps/arm/include/bits/setjmp.h +++ b/sysdeps/arm/include/bits/setjmp.h @@ -30,7 +30,7 @@ # define JMP_BUF_REGLIST {v1-v6, sl, fp} /* Index of __jmp_buf where the sp register resides. */ -# define __JMP_BUF_SP 8 +# define __JMP_BUF_SP 0 #endif #endif /* include/bits/setjmp.h */ diff --git a/sysdeps/arm/setjmp.S b/sysdeps/arm/setjmp.S index b0b45ed..5e55ca5 100644 --- a/sysdeps/arm/setjmp.S +++ b/sysdeps/arm/setjmp.S @@ -17,6 +17,7 @@ . */ #include +#include #include #include #include @@ -27,9 +28,11 @@ ENTRY (__sigsetjmp) #endif mov ip, r0 - /* Save registers */ - sfi_breg ip, \ - stmia \B!, JMP_BUF_REGLIST + /* setjmp probe expects sigsetjmp first argument (4@r0), second + argument (-4@r1), and target address (4@r14), respectively. */ + LIBC_PROBE (setjmp, 3, 4@r0, -4@r1, 4@r14) + + /* Save sp and lr */ #ifdef PTR_MANGLE mov a4, sp PTR_MANGLE2 (a4, a4, a3) @@ -40,6 +43,9 @@ ENTRY (__sigsetjmp) str sp, [ip], #4 str lr, [ip], #4 #endif + /* Save registers */ + sfi_breg ip, \ + stmia \B!, JMP_BUF_REGLIST #if !defined ARM_ASSUME_NO_IWMMXT || defined __SOFTFP__ # define NEED_HWCAP 1