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[209.132.180.131]) by mx.google.com with ESMTPS id n127si68184225pga.323.2016.11.30.23.36.45 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Nov 2016 23:36:45 -0800 (PST) Received-SPF: pass (google.com: domain of gdb-patches-return-135516-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org; spf=pass (google.com: domain of gdb-patches-return-135516-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gdb-patches-return-135516-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:from:date:message-id:subject:to :cc:content-type; q=dns; s=default; b=D85F/9tacF0udQqJEK6LrLETce c2vYQxkgJgbfn9J0XXjmhELaZSH0trBychcRHyunkCVyYmHZMXU/zc0nNLsPOPsV fTznnQwjmPoKAmd1Ud2u9VJ+5ebmJauFyQbjWhRKTmrgrMsUhiUs8/Hh5gMzulAd BgmC1DdONoOApmEjA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:from:date:message-id:subject:to :cc:content-type; s=default; bh=3/Z+W5aZkkGkKa8d/vYtGu8EJa8=; b= MR8iE7D3sZcq5b6h3TH0USYQh5VD2iTmVtu/JuszccGnUNe91/c+RmCdALadboT3 36Xo0jEk8+tsk0txcnSj3bGGephdOcsZdSFUie5lldFxj1bIU5y0ns8Edgf8hKk4 RCAGoSkD3W5KnIleWDz+wY412vEGbU1YJSK1L9LDVsE= Received: (qmail 74958 invoked by alias); 1 Dec 2016 07:36:38 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 74930 invoked by uid 89); 1 Dec 2016 07:36:36 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=sim, Hx-languages-length:1920, emulated, wilson X-HELO: mail-yw0-f176.google.com Received: from mail-yw0-f176.google.com (HELO mail-yw0-f176.google.com) (209.85.161.176) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 01 Dec 2016 07:36:26 +0000 Received: by mail-yw0-f176.google.com with SMTP id t125so177540497ywc.1 for ; Wed, 30 Nov 2016 23:36:26 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=OSmK4enG5w4VXqTZ8K0C9SwGq7KANg4igCM7xQo64XE=; b=e26uEm0akWepPHbnerd5TBdf07Tuy+u17QcfnP/0mtTHhJraCV63z4xcxNbkK7h1oG RF67bIAiFeotzspOH/AAFOCZU1sBdPmee9wkNr2Xakw3yyNV57xab88sp3bV+wTs18Jw RtUIGwm7/oYdaKLfNUZOMyf1LQ3FuV3+t3TkIgFv6mI2H/6inphoNOt/YuAkeJbUoYoO BGjkuga/cUP2kq3SM+RxNeiqA55TiW06vuWuuK1KHwhCBaa2s+0KkJDsX6b3WaXjHb6Z OqBMWayR2a7EX6BtSKcK9Ahui18PtPWby+frdG9Kq12uSG3V0UkhE22MVASpJgCeoylQ fLtA== X-Gm-Message-State: AKaTC00+7nDkvweTOkgn2YebtqZu+MD+Kx5DmVXJxt+H/Cju12dHQTlkXJ6tzBQlVGgqMrT9k2tPby3Ya5QZBLJW X-Received: by 10.13.220.197 with SMTP id f188mr40788810ywe.6.1480577785007; Wed, 30 Nov 2016 23:36:25 -0800 (PST) MIME-Version: 1.0 Received: by 10.129.92.4 with HTTP; Wed, 30 Nov 2016 23:36:24 -0800 (PST) From: Jim Wilson Date: Wed, 30 Nov 2016 23:36:24 -0800 Message-ID: Subject: [PATCH] fix for aarch64 sim FP stur bug To: gdb-patches@sourceware.org Cc: Nick Clifton While debugging a gcc C testsuite failure on the aarch64 simulator, I noticed that the support for FP stur instructions is broken. They accidentally have the two register operands swapped. The problem can be seen by comparing them with the equivalent FP str instructions. I tested the fix by running the gcc C testsuite. I get 3122 unexpected failures without the patch and 2856 unexpected failures with the patch. Jim 2016-11-30 Jim Wilson * sim/aarch64/simulator.c (fsturs): Switch use of rn and st variables. (fsturd, fsturq): Likewise diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index e5ada18..4fa5dc1 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -7497,8 +7497,8 @@ fsturs (sim_cpu *cpu, int32_t offset) unsigned int st = INSTR (4, 0); TRACE_DECODE (cpu, "emulated at line %d", __LINE__); - aarch64_set_mem_u32 (cpu, aarch64_get_reg_u64 (cpu, st, 1) + offset, - aarch64_get_vec_u32 (cpu, rn, 0)); + aarch64_set_mem_u32 (cpu, aarch64_get_reg_u64 (cpu, rn, 1) + offset, + aarch64_get_vec_u32 (cpu, st, 0)); } /* Store 64 bit unscaled signed 9 bit. */ @@ -7509,8 +7509,8 @@ fsturd (sim_cpu *cpu, int32_t offset) unsigned int st = INSTR (4, 0); TRACE_DECODE (cpu, "emulated at line %d", __LINE__); - aarch64_set_mem_u64 (cpu, aarch64_get_reg_u64 (cpu, st, 1) + offset, - aarch64_get_vec_u64 (cpu, rn, 0)); + aarch64_set_mem_u64 (cpu, aarch64_get_reg_u64 (cpu, rn, 1) + offset, + aarch64_get_vec_u64 (cpu, st, 0)); } /* Store 128 bit unscaled signed 9 bit. */ @@ -7522,9 +7522,9 @@ fsturq (sim_cpu *cpu, int32_t offset) FRegister a; TRACE_DECODE (cpu, "emulated at line %d", __LINE__); - aarch64_get_FP_long_double (cpu, rn, & a); + aarch64_get_FP_long_double (cpu, st, & a); aarch64_set_mem_long_double (cpu, - aarch64_get_reg_u64 (cpu, st, 1) + aarch64_get_reg_u64 (cpu, rn, 1) + offset, a); }