From patchwork Mon Dec 5 03:43:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 86493 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp1293225qgi; Sun, 4 Dec 2016 19:45:51 -0800 (PST) X-Received: by 10.84.217.203 with SMTP id d11mr36749537plj.164.1480909551250; Sun, 04 Dec 2016 19:45:51 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id m25si13113778pli.104.2016.12.04.19.45.50 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 04 Dec 2016 19:45:51 -0800 (PST) Received-SPF: pass (google.com: domain of gdb-patches-return-135626-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org; spf=pass (google.com: domain of gdb-patches-return-135626-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gdb-patches-return-135626-patch=linaro.org@sourceware.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-type; q=dns; s=default; b=XeOr RnmUPEme/CKhEwKAkU6I3ihxqUE41M71yql13p2uHCLTnYyCYmpH6j2zkV6YyO3f tkRqZRPUWMcnyOItVmsdgNAcPnwKOhiOtOwUUYV91XBJiD/cI/QVCr2TCVSDZQbs B8+rhC1MBr6TqxjDJ93LC2c3lsoKmiw47qn27bU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-type; s=default; bh=cXENJW0xWb J5e+SX95NpSY7WUB4=; b=n7xmcu/yF23DxhkfOrdJfoSduzrls8tTP6UJTWxjEv zluytBVIIAw3yklCA0ZfdcyA7oNj6iO4bnLVIFeyZFgpoRhvtHouBcA5XNZ2KEMy Oh1SnReRR7dqgR2RF7JtMoGKiRrEw/BbSnUWRN9U+REwY443FjoDKX//g7RpjX9X w= Received: (qmail 82460 invoked by alias); 5 Dec 2016 03:45:40 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 81486 invoked by uid 89); 5 Dec 2016 03:44:00 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=quit, U*vapier, sk:vapier@, sk:vapier X-HELO: mail-yw0-f178.google.com Received: from mail-yw0-f178.google.com (HELO mail-yw0-f178.google.com) (209.85.161.178) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 05 Dec 2016 03:43:49 +0000 Received: by mail-yw0-f178.google.com with SMTP id i145so248089589ywg.2 for ; Sun, 04 Dec 2016 19:43:49 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=/WxPYWYC+1UJlPfzyyJkQ+Z5RtNjsFn6OlkSHIecm9E=; b=MBsx9xVaYAIjmDt74WUfam0wBwZw9DDH+TrCa1cR8RsUFjnZ3oSVUriF7tan5uO8y2 L0GJVcbHeK3OE5IUNQmEIa0d9L+LjpfqjUROaN/AG+6L9rCF4rlLH6lWVsDzQzYhZrFS ItD6eiG0jXTMI1c1MUHigHLUcq6Rf+CR+DH9UTVGkrF/NeuaQIIz38VSxIZZQX+4bEEY wxxV2CaQCC75SJiwAbb50ojxdnWUaAko6I3ZKcuUszE4ET/HZN+CcXsvuQyThaCVY4O3 yIQAUQQlDfdyoyJ7UXbM9lCDVIw3vAJH0O2puEk42xU45xlTjFOn0O9GPThqsd5JrsX9 vsTA== X-Gm-Message-State: AKaTC01H6aIbagdimrM6VNkvH5YSp37ajHT7IfxWJZJ/ETPFHy6mv/Vm1ezLoF0Ae7DsVkMi3bvxJFhEUZW+zjY6 X-Received: by 10.129.40.149 with SMTP id o143mr52690501ywo.106.1480909427787; Sun, 04 Dec 2016 19:43:47 -0800 (PST) MIME-Version: 1.0 Received: by 10.129.92.4 with HTTP; Sun, 4 Dec 2016 19:43:47 -0800 (PST) In-Reply-To: References: From: Jim Wilson Date: Sun, 4 Dec 2016 19:43:47 -0800 Message-ID: Subject: Re: [PATCH] fix for aarch64 sim tbnz bug To: Mike Frysinger Cc: "gdb-patches@sourceware.org" , Nick Clifton On Fri, Dec 2, 2016 at 1:31 AM, Mike Frysinger wrote: > can we please start getting tests added to sim too ? using gcc > indirectly to validate the sim is a bit un The GCC testsuite is the part that I care most about, but it does make sense for me to be adding simulator tests. There are currently no interesting aarch64 tests, so it isn't clear if there is any particular style I should be using. So I just chose a style that seemed OK to me. I have tests for the last two simulator patches I contributed. I verified that the tests work with current sources and fail without my two patches. I had to make a few fixes to the existing testsuite.inc file. I moved .Lpass and .Lfail out of the pass and fail macros, as otherwise I end up with duplicate definitions. I also changed fail to return non-zero, because it should. I find it confusing to manually run a testcase and see it print fail, and then return a zero exit code. Jim PS set_flags_for_add64 is broken, which causes adds and cmn to fail. I have a fix, and this will be my next aarch64 sim patch, but I haven't written a testcase yet. 2016-12-04 Jim Wilson sim/testsuite/sim/aarch64 * testutils.inc (pass): Move .Lpass outside macro. (fail): Move .Lfail outside macro. Return 1 instead of 0. * fstur.s: New. * tbnz.s: New. diff --git a/sim/testsuite/sim/aarch64/fstur.s b/sim/testsuite/sim/aarch64/fstur.s new file mode 100644 index 0000000..2206ae5 --- /dev/null +++ b/sim/testsuite/sim/aarch64/fstur.s @@ -0,0 +1,136 @@ +# mach: aarch64 + +# Check the FP store unscaled offset instructions: fsturs, fsturd, fsturq. +# Check the values -1, and XXX_MAX, which tests all bits. +# Check with offsets -256 and 255, which tests all bits. +# Also tests the FP load unscaled offset instructions: fldurs, fldurd, fldurq. + +.include "testutils.inc" + + .data +fm1: + .word 3212836864 +fmax: + .word 2139095039 +ftmp: + .word 0 + +dm1: + .word 0 + .word -1074790400 +dmax: + .word 4294967295 + .word 2146435071 +dtmp: + .word 0 + .word 0 + +ldm1: + .word 0 + .word 0 + .word 0 + .word -1073807360 +ldmax: + .word 4294967295 + .word 4294967295 + .word 4294967295 + .word 2147418111 +ldtmp: + .word 0 + .word 0 + .word 0 + .word 0 + + start + adrp x1, ftmp + add x1, x1, :lo12:ftmp + + adrp x0, fm1 + add x0, x0, :lo12:fm1 + sub x5, x0, #255 + sub x6, x1, #255 + movi d2, #0 + ldur s2, [x5, #255] + stur s2, [x6, #255] + ldr w3, [x0] + ldr w4, [x1] + cmp w3, w4 + bne .Lfailure + + adrp x0, fmax + add x0, x0, :lo12:fmax + add x5, x0, #256 + add x6, x1, #256 + movi d2, #0 + ldur s2, [x5, #-256] + stur s2, [x6, #-256] + ldr w3, [x0] + ldr w4, [x1] + cmp w3, w4 + bne .Lfailure + + adrp x1, dtmp + add x1, x1, :lo12:dtmp + + adrp x0, dm1 + add x0, x0, :lo12:dm1 + sub x5, x0, #255 + sub x6, x1, #255 + movi d2, #0 + ldur d2, [x5, #255] + stur d2, [x6, #255] + ldr x3, [x0] + ldr x4, [x1] + cmp x3, x4 + bne .Lfailure + + adrp x0, dmax + add x0, x0, :lo12:dmax + add x5, x0, #256 + add x6, x1, #256 + movi d2, #0 + ldur d2, [x5, #-256] + stur d2, [x6, #-256] + ldr x3, [x0] + ldr x4, [x1] + cmp x3, x4 + bne .Lfailure + + adrp x1, ldtmp + add x1, x1, :lo12:ldtmp + + adrp x0, ldm1 + add x0, x0, :lo12:ldm1 + sub x5, x0, #255 + sub x6, x1, #255 + movi v2.2d, #0 + ldur q2, [x5, #255] + stur q2, [x6, #255] + ldr x3, [x0] + ldr x4, [x1] + cmp x3, x4 + bne .Lfailure + ldr x3, [x0, 8] + ldr x4, [x1, 8] + cmp x3, x4 + bne .Lfailure + + adrp x0, ldmax + add x0, x0, :lo12:ldmax + add x5, x0, #256 + add x6, x1, #256 + movi v2.2d, #0 + ldur q2, [x5, #-256] + stur q2, [x6, #-256] + ldr x3, [x0] + ldr x4, [x1] + cmp x3, x4 + bne .Lfailure + ldr x3, [x0, 8] + ldr x4, [x1, 8] + cmp x3, x4 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/sim/aarch64/tbnz.s b/sim/testsuite/sim/aarch64/tbnz.s new file mode 100644 index 0000000..2416101 --- /dev/null +++ b/sim/testsuite/sim/aarch64/tbnz.s @@ -0,0 +1,55 @@ +# mach: aarch64 + +# Check the test-bit-and-branch instructions: tbnz, and tbz. +# We check the edge condition bit positions: 0, 1<<31, 1<<32, 1<<63. + +.include "testutils.inc" + + start + mov x0, #1 + tbnz x0, #0, .L1 + fail +.L1: + tbz x0, #0, .Lfailure + mov x0, #0xFFFFFFFFFFFFFFFE + tbnz x0, #0, .Lfailure + tbz x0, #0, .L2 + fail +.L2: + + mov x0, #0x80000000 + tbnz x0, #31, .L3 + fail +.L3: + tbz x0, #31, .Lfailure + mov x0, #0xFFFFFFFF7FFFFFFF + tbnz x0, #31, .Lfailure + tbz x0, #31, .L4 + fail +.L4: + + mov x0, #0x100000000 + tbnz x0, #32, .L5 + fail +.L5: + tbz x0, #32, .Lfailure + mov x0, #0xFFFFFFFEFFFFFFFF + tbnz x0, #32, .Lfailure + tbz x0, #32, .L6 + fail +.L6: + + mov x0, #0x8000000000000000 + tbnz x0, #63, .L7 + fail +.L7: + tbz x0, #63, .Lfailure + mov x0, #0x7FFFFFFFFFFFFFFF + tbnz x0, #63, .Lfailure + tbz x0, #63, .L8 + fail +.L8: + + pass +.Lfailure: + fail diff --git a/sim/testsuite/sim/aarch64/testutils.inc b/sim/testsuite/sim/aarch64/testutils.inc index c8897aa..99057af 100644 --- a/sim/testsuite/sim/aarch64/testutils.inc +++ b/sim/testsuite/sim/aarch64/testutils.inc @@ -43,11 +43,11 @@ swiwrite 5 exit 0 + .endm .data .Lpass: .asciz "pass\n" - .endm # MACRO: fail # Write 'fail' to stdout and quit @@ -56,12 +56,12 @@ adrp x1, .Lfail add x1, x1, :lo12:.Lfail swiwrite 5 - exit 0 + exit 1 + .endm .data .Lfail: .asciz "fail\n" - .endm # MACRO: start # All assembler tests should start with a call to "start"