diff --git a/gdb/testsuite/gdb.reverse/aarch64-test-rrp.exp b/gdb/testsuite/gdb.reverse/aarch64-test-rrp.exp
new file mode 100644
index 0000000..ddf36d5
--- /dev/null
+++ b/gdb/testsuite/gdb.reverse/aarch64-test-rrp.exp
@@ -0,0 +1,234 @@
+# Copyright (C) 2012-2015 Free Software Foundation, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+if ![supports_reverse] {
+    return
+}
+
+# Test aarch64 instruction recording.
+
+if {![istarget "aarch64*-*-*"]} then {
+    verbose "Skipping aarch64 instruction recording tests."
+    return
+}
+
+# Compile .S File.
+
+proc CompileFile {} {
+
+  global objdir
+  global subdir
+  global srcdir
+
+  set testfile "aarch64-test-rrp"
+  set srcfile ${testfile}.S
+  set binfile ${objdir}/${subdir}/${testfile}
+
+  set additional_flags "-Wa,-g"
+
+  if { [gdb_compile "${srcdir}/${subdir}/${srcfile}" "${binfile}" executable [list debug $additional_flags]] != "" } {
+      untested aarch64-test-rrp.exp
+      return -1
+  }
+
+  # Get things started.
+
+  clean_restart ${testfile}
+
+  # Setting breakpoint at main
+
+  if ![runto_main] then {
+      fail "Can't run to main"
+      return 0
+  }
+}
+
+# Return the List of register values required. 
+
+proc Read_Registers {Reg_li} {
+  global gdb_prompt
+  upvar 1 $Reg_li Reg_list
+  set Reg_value_list {}
+
+  foreach index $Reg_list {
+      if { $index != {} } {
+          send_gdb "info registers $index \n"
+          gdb_expect {
+             -re "($index +.*\n)(.*)(\n$gdb_prompt)" {
+             lappend Reg_value_list $expect_out(2,string)
+             }
+          }
+      }
+  }
+    return $Reg_value_list
+}
+
+# Verifying Registers before and after reverse.
+
+proc verify_Registers {Reg_names Reg_values instruction} {
+  global gdb_prompt
+  upvar 1 $Reg_names reg_names
+  upvar 1 $Reg_values reg_values
+  set ind 0
+
+  foreach index $reg_names {
+      if { $index != {} } {
+          set temp_value [lindex $reg_values $ind]
+          incr ind
+          send_gdb "info registers $index \n"
+          gdb_expect {
+             -re "($index +.*\n)(.*)(\n$gdb_prompt)" {
+              if {[string equal "$temp_value" "$expect_out(2,string)"]} {
+                  pass "Register $index preserved in $instruction"
+              } else {
+                  fail "Register $index corrupted in $instruction"
+              }
+             }
+          }
+      }
+  }
+}
+
+# Read Byte_Length memory from mem_address.
+
+proc Read_Memory {mem_address Byte_Length} {
+    set output {}
+    set str [format x/%sxb%s$mem_address $Byte_Length " "]
+    send_gdb "$str \n"
+        gdb_expect {
+           -re {..*} {
+               append output $expect_out(0,string)
+               exp_continue
+            }
+        }
+    return $output
+}
+
+
+proc verify_Memory {mem_before mem_after instruction} {
+
+  if {[string equal "$mem_before" "$mem_after"]} {
+      pass "Memory preserved in $instruction"
+  } else {
+      fail "Memory corrupted in $instruction"
+  }
+}
+
+# Run the instruction and record the registers and memory.
+
+proc Run_Test {Label_start Label_end Reg_list Mem_address Wordcount instruction} {
+
+  upvar 1 $Reg_list reg_list
+
+  gdb_test "break $Label_start"
+  gdb_test "continue"
+
+  # Reading Registers and Memory before reversing.
+
+  set reg_before [Read_Registers reg_list]
+
+  if { [lindex $Mem_address 0] != {} } {
+      set mem_before [Read_Memory Mem_address Wordcount]
+  }
+
+  # Activate process record/replay.
+  gdb_test "record"
+
+  gdb_test "break $Label_end"
+  gdb_test "continue"
+
+  gdb_test "reverse-continue"
+
+  # Verify if Register values are preserved after Reverse.
+  if { [lindex $reg_list 0] != {} } {
+      verify_Registers reg_list reg_before "$instruction"
+  }
+  # Verify if Memory is restored after Reverse.
+  if { [lindex $Mem_address 0] != {} } {
+      set mem_after [Read_Memory Mem_address Wordcount]
+  }
+}
+
+# Generates .S file/ compile/ run.
+
+proc run_rrp_tests {} {
+
+  global subdir
+  global srcdir
+
+  set testfile "aarch64-test-rrp"
+  set srcfile ${testfile}.S
+
+  # Reading from instructions File.
+  set file_ins [open "$srcdir/$subdir/aarch64-test-rrp.txt" "r"]
+  set ins_data [read $file_ins]
+  set ins_data [split $ins_data "\n"]
+
+      for {set i 0} {$i < [llength $ins_data]-1} {incr i} { 
+          if {[string index [lindex $ins_data $i] 0] != "@" \
+              && [string index [lindex $ins_data $i] 0] != ""} {
+
+              # Generating .S File.
+              set Sfile [open $srcdir/$subdir/$srcfile "w+"]
+
+              # appending Lines in Array. 
+              puts -nonewline $Sfile "\
+	.cpu generic
+	.text
+	.align 2
+	.global main
+	.type main, %function
+main:
+	stp x29, x30, \[sp, -16\]!
+	add x29, sp, 0
+	bl Start
+	mov w0, 0
+	ldp x29, x30, \[sp\], 16
+	ret
+	.align 2
+	.global Start
+	.type Start, %function
+Start:
+	mov w0, w0
+	mov w0, w0
+        [lindex $ins_data $i]
+	mov w0, w0
+End:
+	mov w0, 0
+	ret
+"
+              close $Sfile
+              set line [lindex $ins_data $i]
+              incr i
+              set regs_mem [split [lindex $ins_data $i] ":"]   
+              set registers [split [lindex $regs_mem 0], ","]
+              set mem [split [lindex $regs_mem 1], ","]
+              if { [lindex $mem 0] != {} } {
+                  set memaddr [lindex $mem 0]
+                  set bytesize [lindex $mem 1]
+              } else {
+                  set bytesize {}
+                  set memaddr {}
+              }
+              # Compile .S File.
+              CompileFile
+
+              # Run the instruction and verify the registers and memory after reverse.
+              Run_Test "Start" "End" registers "$memaddr" "$bytesize" "$line"
+         }
+      }
+}
+
+run_rrp_tests
diff --git a/gdb/testsuite/gdb.reverse/aarch64-test-rrp.txt b/gdb/testsuite/gdb.reverse/aarch64-test-rrp.txt
new file mode 100644
index 0000000..5b67661
--- /dev/null
+++ b/gdb/testsuite/gdb.reverse/aarch64-test-rrp.txt
@@ -0,0 +1,2115 @@
+@ load and STORE
+@-------------------------------------------------------
+ld1 { v1.8b }, [x0]
+v1:
+ld1 { v2.8b, v3.8b }, [x0]
+v2,v3:
+ld1 { v3.8b, v4.8b, v5.8b }, [x0]
+v3,v4,v5:
+ld1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x0]
+v4,v5,v6,v7:
+ld1 { v1.16b }, [x0]
+v1:
+ld1 { v2.16b, v3.16b }, [x0]
+v2,v3:
+ld1 { v3.16b, v4.16b, v5.16b }, [x0]
+v3,v4,v5:
+ld1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x0]
+v4,v5,v6,v7:
+ld1 { v1.4h }, [x0]
+v1:
+ld1 { v2.4h, v3.4h }, [x0]
+v2,v3:
+ld1 { v3.4h, v4.4h, v5.4h }, [x0]
+v3,v4,v5:
+ld1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x0]
+v7,v8,v9,v10:
+ld1 { v1.8h }, [x0]
+v1:
+ld1 { v2.8h, v3.8h }, [x0]
+v2,v3:
+ld1 { v3.8h, v4.8h, v5.8h }, [x0]
+v3,v4,v5:
+ld1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x0]
+v7,v8,v9,v10:
+ld1 { v1.2s }, [x0]
+v1:
+ld1 { v2.2s, v3.2s }, [x0]
+v2,v3:
+ld1 { v3.2s, v4.2s, v5.2s }, [x0]
+v3,v4,v5:
+ld1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x0]
+v7,v8,v9,v10:
+ld1 { v1.4s }, [x0]
+v1:
+ld1 { v2.4s, v3.4s }, [x0]
+v2,v3:
+ld1 { v3.4s, v4.4s, v5.4s }, [x0]
+v3,v4,v5:
+ld1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x0]
+v7,v8,v9,v10:
+ld1 { v1.1d }, [x0]
+v1:
+ld1 { v2.1d, v3.1d }, [x0]
+v2,v3:
+ld1 { v3.1d, v4.1d, v5.1d }, [x0]
+v3,v4,v5:
+ld1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x0]
+v7,v8,v9,v10:
+ld1 { v1.2d }, [x0]
+v1:
+ld1 { v2.2d, v3.2d }, [x0]
+v2,v3:
+ld1 { v3.2d, v4.2d, v5.2d }, [x0]
+v3,v4,v5:
+ld1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x0]
+v7,v8,v9,v10:
+
+ld2 { v3.8b, v4.8b }, [x19]
+v3,v4:
+ld2 { v3.16b, v4.16b }, [x19]
+v3,v4:
+ld2 { v3.4h, v4.4h }, [x19]
+v3,v4:
+ld2 { v3.8h, v4.8h }, [x19]
+v3,v4:
+ld2 { v3.2s, v4.2s }, [x19]
+v3,v4:
+ld2 { v3.4s, v4.4s }, [x19]
+v3,v4:
+ld2 { v3.2d, v4.2d }, [x19]
+v3,v4:
+
+ld3 { v2.8b, v3.8b, v4.8b }, [x19]
+v2,v3,v4:
+ld3 { v2.16b, v3.16b, v4.16b }, [x19]
+v2,v3,v4:
+ld3 { v2.4h, v3.4h, v4.4h }, [x19]
+v2,v3,v4:
+ld3 { v2.8h, v3.8h, v4.8h }, [x19]
+v2,v3,v4:
+ld3 { v2.2s, v3.2s, v4.2s }, [x19]
+v2,v3,v4:
+ld3 { v2.4s, v3.4s, v4.4s }, [x19]
+v2,v3,v4:
+ld3 { v2.2d, v3.2d, v4.2d }, [x19]
+v2,v3,v4:
+
+ld4 { v2.8b, v3.8b, v4.8b, v5.8b }, [x19]
+v2,v3,v4,v5:
+ld4 { v2.16b, v3.16b, v4.16b, v5.16b }, [x19]
+v2,v3,v4,v5:
+ld4 { v2.4h, v3.4h, v4.4h, v5.4h }, [x19]
+v2,v3,v4,v5:
+ld4 { v2.8h, v3.8h, v4.8h, v5.8h }, [x19]
+v2,v3,v4,v5:
+ld4 { v2.2s, v3.2s, v4.2s, v5.2s }, [x19]
+v2,v3,v4,v5:
+ld4 { v2.4s, v3.4s, v4.4s, v5.4s }, [x19]
+v2,v3,v4,v5:
+ld4 { v2.2d, v3.2d, v4.2d, v5.2d }, [x19]
+v2,v3,v4,v5:
+
+ld1 { v1.8b }, [x0], x15
+v1:
+ld1 { v2.8b, v3.8b }, [x0], x15
+v2,v3:
+ld1 { v3.8b, v4.8b, v5.8b }, [x0], x15
+v2,v3,v5:
+ld1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x0], x15
+v4,v5,v6,v7:
+ld1 { v1.16b }, [x0], x15
+v1:
+ld1 { v2.16b, v3.16b }, [x0], x15
+v2,v3:
+ld1 { v3.16b, v4.16b, v5.16b }, [x0], x15
+v3,v4,v5:
+ld1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x0], x15
+v4,v5,v6,v7:
+ld1 { v1.4h }, [x0], x15
+v1:
+ld1 { v2.4h, v3.4h }, [x0], x15
+v2,v3:
+ld1 { v3.4h, v4.4h, v5.4h }, [x0], x15
+v3,v4,v5:
+ld1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x0], x15
+v7,v8,v9,v10:
+ld1 { v1.8h }, [x0], x15
+v1:
+ld1 { v2.8h, v3.8h }, [x0], x15
+v2,v3:
+ld1 { v3.8h, v4.8h, v5.8h }, [x0], x15
+v3,v4,v5:
+ld1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x0], x15
+v7,v8,v9,v10:
+ld1 { v1.2s }, [x0], x15
+v1:
+ld1 { v2.2s, v3.2s }, [x0], x15
+v2,v3:
+ld1 { v3.2s, v4.2s, v5.2s }, [x0], x15
+v3,v4,v5:
+ld1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x0], x15
+v7,v8,v9,v10:
+ld1 { v1.4s }, [x0], x15
+v1:
+ld1 { v2.4s, v3.4s }, [x0], x15
+v2,v3:
+ld1 { v3.4s, v4.4s, v5.4s }, [x0], x15
+v3,v4,v5:
+ld1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x0], x15
+v7,v8,v9,v10:
+ld1 { v1.1d }, [x0], x15
+v1:
+ld1 { v2.1d, v3.1d }, [x0], x15
+v2,v3:
+ld1 { v3.1d, v4.1d, v5.1d }, [x0], x15
+v3,v4,v5:
+ld1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x0], x15
+v7,v8,v9,v10:
+ld1 { v1.2d }, [x0], x15
+v1:
+ld1 { v2.2d, v3.2d }, [x0], x15
+v2,v3:
+ld1 { v3.2d, v4.2d, v5.2d }, [x0], x15
+v3,v4,v5:
+ld1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x0], x15
+v7,v8,v9,v10:
+
+ld1 { v1.8b }, [x0], #8
+v1:
+ld1 { v2.8b, v3.8b }, [x0], #16
+v2,v3:
+ld1 { v3.8b, v4.8b, v5.8b }, [x0], #24
+v3,v4,v5:
+ld1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x0], #32
+v4,v5,v6,v7:
+ld1 { v1.16b }, [x0], #16
+v1:
+ld1 { v2.16b, v3.16b }, [x0], #32
+v2,v3:
+ld1 { v3.16b, v4.16b, v5.16b }, [x0], #48
+v3,v4,v5:
+ld1 { v4.16b, v5.16b, v6.16b, v7.16b }, [x0], #64
+v4,v5,v6,v7:
+ld1 { v1.4h }, [x0], #8
+v1:
+ld1 { v2.4h, v3.4h }, [x0], #16
+v2,v3:
+ld1 { v3.4h, v4.4h, v5.4h }, [x0], #24
+v3,v4,v5:
+ld1 { v7.4h, v8.4h, v9.4h, v10.4h }, [x0], #32
+v7,v8,v9,v10:
+ld1 { v1.8h }, [x0], #16
+v1:
+ld1 { v2.8h, v3.8h }, [x0], #32
+v2,v3:
+ld1 { v3.8h, v4.8h, v5.8h }, [x0], #48
+v3,v4,v5:
+ld1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x0], #64
+v7,v8,v9,v10:
+ld1 { v1.2s }, [x0], #8
+v1:
+ld1 { v2.2s, v3.2s }, [x0], #16
+v2,v3:
+ld1 { v3.2s, v4.2s, v5.2s }, [x0], #24
+v3,v4,v5:
+ld1 { v7.2s, v8.2s, v9.2s, v10.2s }, [x0], #32
+v7,v8,v9,v10:
+ld1 { v1.4s }, [x0], #16
+v1:
+ld1 { v2.4s, v3.4s }, [x0], #32
+v2,v3:
+ld1 { v3.4s, v4.4s, v5.4s }, [x0], #48
+v3,v4,v5:
+ld1 { v7.4s, v8.4s, v9.4s, v10.4s }, [x0], #64
+v7,v8,v9,v10:
+ld1 { v1.1d }, [x0], #8
+v1:
+ld1 { v2.1d, v3.1d }, [x0], #16
+v2,v3:
+ld1 { v3.1d, v4.1d, v5.1d }, [x0], #24
+v3,v4,v5:
+ld1 { v7.1d, v8.1d, v9.1d, v10.1d }, [x0], #32
+v7,v8,v9,v10:
+ld1 { v1.2d }, [x0], #16
+v1:
+ld1 { v2.2d, v3.2d }, [x0], #32
+v2,v3:
+ld1 { v3.2d, v4.2d, v5.2d }, [x0], #48
+v3,v4,v5:
+ld1 { v7.2d, v8.2d, v9.2d, v10.2d }, [x0], #64
+v7,v8,v9,v10:
+
+ld2 { v2.8b, v3.8b }, [x0], x15
+v2,v3:
+ld2 { v2.16b, v3.16b }, [x0], x15
+v2,v3:
+ld2 { v2.4h, v3.4h }, [x0], x15
+v2,v3:
+ld2 { v2.8h, v3.8h }, [x0], x15
+v2,v3:
+ld2 { v2.2s, v3.2s }, [x0], x15
+v2,v3:
+ld2 { v2.4s, v3.4s }, [x0], x15
+v2,v3:
+ld2 { v2.2d, v3.2d }, [x0], x15
+v2,v3:
+
+ld2 { v2.8b, v3.8b }, [x0], #16
+v2,v3:
+ld2 { v2.16b, v3.16b }, [x0], #32
+v2,v3:
+ld2 { v2.4h, v3.4h }, [x0], #16
+v2,v3:
+ld2 { v2.8h, v3.8h }, [x0], #32
+v2,v3:
+ld2 { v2.2s, v3.2s }, [x0], #16
+v2,v3:
+ld2 { v2.4s, v3.4s }, [x0], #32
+v2,v3:
+ld2 { v2.2d, v3.2d }, [x0], #32
+v2,v3:
+
+ld3 { v3.8b, v4.8b, v5.8b }, [x0], x15
+v3,v4,v5:
+ld3 { v3.16b, v4.16b, v5.16b }, [x0], x15
+v3,v4,v5:
+ld3 { v3.4h, v4.4h, v5.4h }, [x0], x15
+v3,v4,v5:
+ld3 { v3.8h, v4.8h, v5.8h }, [x0], x15
+v3,v4,v5:
+ld3 { v3.2s, v4.2s, v5.2s }, [x0], x15
+v3,v4,v5:
+ld3 { v3.4s, v4.4s, v5.4s }, [x0], x15
+v3,v4,v5:
+ld3 { v3.2d, v4.2d, v5.2d }, [x0], x15
+v3,v4,v5:
+
+ld3 { v3.8b, v4.8b, v5.8b }, [x0], #24
+v3,v4,v5:
+ld3 { v3.16b, v4.16b, v5.16b }, [x0], #48
+v3,v4,v5:
+ld3 { v3.4h, v4.4h, v5.4h }, [x0], #24
+v3,v4,v5:
+ld3 { v3.8h, v4.8h, v5.8h }, [x0], #48
+v3,v4,v5:
+ld3 { v3.2s, v4.2s, v5.2s }, [x0], #24
+v3,v4,v5:
+ld3 { v3.4s, v4.4s, v5.4s }, [x0], #48
+v3,v4,v5:
+ld3 { v3.2d, v4.2d, v5.2d }, [x0], #48
+v3,v4,v5:
+
+ld4 { v4.8b, v5.8b, v6.8b, v7.8b }, [x0], x15
+v4,v5,v6,v7:
+ld4 { v4.16b, v5.16b, v6.16b, v7.16b }, [x0], x15
+v4,v5,v6,v7:
+ld4 { v7.4h, v8.4h, v9.4h, v10.4h }, [x0], x15
+v7,v8,v9,v10:
+ld4 { v7.8h, v8.8h, v9.8h, v10.8h }, [x0], x15
+v7,v8,v9,v10:
+ld4 { v7.2s, v8.2s, v9.2s, v10.2s }, [x0], x15
+v7,v8,v9,v10:
+ld4 { v7.4s, v8.4s, v9.4s, v10.4s }, [x0], x15
+v7,v8,v9,v10:
+ld4 { v7.2d, v8.2d, v9.2d, v10.2d }, [x0], x15
+v7,v8,v9,v10:
+
+ld4 { v4.8b, v5.8b, v6.8b, v7.8b }, [x0], #32
+v4,v5,v6,v7:
+ld4 { v4.16b, v5.16b, v6.16b, v7.16b }, [x0], #64
+v4,v5,v6,v7:
+ld4 { v7.4h, v8.4h, v9.4h, v10.4h }, [x0], #32
+v7,v8,v9,v10:
+ld4 { v7.8h, v8.8h, v9.8h, v10.8h }, [x0], #64
+v7,v8,v9,v10:
+ld4 { v7.2s, v8.2s, v9.2s, v10.2s }, [x0], #32
+v7,v8,v9,v10:
+ld4 { v7.4s, v8.4s, v9.4s, v10.4s }, [x0], #64
+v7,v8,v9,v10:
+ld4 { v7.2d, v8.2d, v9.2d, v10.2d }, [x0], #64
+v7,v8,v9,v10:
+
+ld1r { v12.8b }, [x2]
+v12:
+ld1r { v12.8b }, [x2], x3
+v12:
+ld1r { v12.16b }, [x2]
+v12:
+ld1r { v12.16b }, [x2], x3
+v12:
+ld1r { v12.4h }, [x2]
+v12:
+ld1r { v12.4h }, [x2], x3
+v12:
+ld1r { v12.8h }, [x2]
+v12:
+ld1r { v12.8h }, [x2], x3
+v12:
+ld1r { v12.2s }, [x2]
+v12:
+ld1r { v12.2s }, [x2], x3
+v12:
+ld1r { v12.4s }, [x2]
+v12:
+ld1r { v12.4s }, [x2], x3
+v12:
+ld1r { v12.1d }, [x2]
+v12:
+ld1r { v12.1d }, [x2], x3
+v12:
+ld1r { v12.2d }, [x2]
+v12:
+ld1r { v12.2d }, [x2], x3
+v12:
+ld1r { v12.8b }, [x2], #1
+v12:
+ld1r { v12.16b }, [x2], #1
+v12:
+ld1r { v12.4h }, [x2], #2
+v12:
+ld1r { v12.8h }, [x2], #2
+v12:
+ld1r { v12.2s }, [x2], #4
+v12:
+ld1r { v12.4s }, [x2], #4
+v12:
+ld1r { v12.1d }, [x2], #8
+v12:
+ld1r { v12.2d }, [x2], #8
+v12:
+ld2r { v3.8b, v4.8b }, [x2]
+v3,v4:
+ld2r { v3.8b, v4.8b }, [x2], x3
+v3,v4:
+ld2r { v3.16b, v4.16b }, [x2]
+v3,v4:
+ld2r { v3.16b, v4.16b }, [x2], x3
+v3,v4:
+ld2r { v3.4h, v4.4h }, [x2]
+v3,v4:
+ld2r { v3.4h, v4.4h }, [x2], x3
+v3,v4:
+ld2r { v3.8h, v4.8h }, [x2]
+v3,v4:
+ld2r { v3.8h, v4.8h }, [x2], x3
+v3,v4:
+ld2r { v3.2s, v4.2s }, [x2]
+v3,v4:
+ld2r { v3.2s, v4.2s }, [x2], x3
+v3,v4:
+ld2r { v3.4s, v4.4s }, [x2]
+v3,v4:
+ld2r { v3.4s, v4.4s }, [x2], x3
+v3,v4:
+ld2r { v3.1d, v4.1d }, [x2]
+v3,v4:
+ld2r { v3.1d, v4.1d }, [x2], x3
+v3,v4:
+ld2r { v3.2d, v4.2d }, [x2]
+v3,v4:
+ld2r { v3.2d, v4.2d }, [x2], x3
+v3,v4:
+ld2r { v3.8b, v4.8b }, [x2], #2
+v3,v4:
+ld2r { v3.16b, v4.16b }, [x2], #2
+v3,v4:
+ld2r { v3.4h, v4.4h }, [x2], #4
+v3,v4:
+ld2r { v3.8h, v4.8h }, [x2], #4
+v3,v4:
+ld2r { v3.2s, v4.2s }, [x2], #8
+v3,v4:
+ld2r { v3.4s, v4.4s }, [x2], #8
+v3,v4:
+ld2r { v3.1d, v4.1d }, [x2], #16
+v3,v4:
+ld2r { v3.2d, v4.2d }, [x2], #16
+v3,v4:
+ld3r { v2.8b, v3.8b, v4.8b }, [x2]
+v2,v3,v4:
+ld3r { v2.8b, v3.8b, v4.8b }, [x2], x3
+v2,v3,v4:
+ld3r { v2.16b, v3.16b, v4.16b }, [x2]
+v2,v3,v4:
+ld3r { v2.16b, v3.16b, v4.16b }, [x2], x3
+v2,v3,v4:
+ld3r { v2.4h, v3.4h, v4.4h }, [x2]
+v2,v3,v4:
+ld3r { v2.4h, v3.4h, v4.4h }, [x2], x3
+v2,v3,v4:
+ld3r { v2.8h, v3.8h, v4.8h }, [x2]
+v2,v3,v4:
+ld3r { v2.8h, v3.8h, v4.8h }, [x2], x3
+v2,v3,v4:
+ld3r { v2.2s, v3.2s, v4.2s }, [x2]
+v2,v3,v4:
+ld3r { v2.2s, v3.2s, v4.2s }, [x2], x3
+v2,v3,v4:
+ld3r { v2.4s, v3.4s, v4.4s }, [x2]
+v2,v3,v4:
+ld3r { v2.4s, v3.4s, v4.4s }, [x2], x3
+v2,v3,v4:
+ld3r { v2.1d, v3.1d, v4.1d }, [x2]
+v2,v3,v4:
+ld3r { v2.1d, v3.1d, v4.1d }, [x2], x3
+v2,v3,v4:
+ld3r { v2.2d, v3.2d, v4.2d }, [x2]
+v2,v3,v4:
+ld3r { v2.2d, v3.2d, v4.2d }, [x2], x3
+v2,v3,v4:
+ld3r { v2.8b, v3.8b, v4.8b }, [x2], #3
+v2,v3,v4:
+ld3r { v2.16b, v3.16b, v4.16b }, [x2], #3
+v2,v3,v4:
+ld3r { v2.4h, v3.4h, v4.4h }, [x2], #6
+v2,v3,v4:
+ld3r { v2.8h, v3.8h, v4.8h }, [x2], #6
+v2,v3,v4:
+ld3r { v2.2s, v3.2s, v4.2s }, [x2], #12
+v2,v3,v4:
+ld3r { v2.4s, v3.4s, v4.4s }, [x2], #12
+v2,v3,v4:
+ld3r { v2.1d, v3.1d, v4.1d }, [x2], #24
+v2,v3,v4:
+ld3r { v2.2d, v3.2d, v4.2d }, [x2], #24
+v2,v3,v4:
+ld4r { v2.8b, v3.8b, v4.8b, v5.8b }, [x2]
+v2,v3,v4,v5:
+ld4r { v2.8b, v3.8b, v4.8b, v5.8b }, [x2], x3
+v2,v3,v4,v5:
+ld4r { v2.16b, v3.16b, v4.16b, v5.16b }, [x2]
+v2,v3,v4,v5:
+ld4r { v2.16b, v3.16b, v4.16b, v5.16b }, [x2], x3
+v2,v3,v4,v5:
+ld4r { v2.4h, v3.4h, v4.4h, v5.4h }, [x2]
+v2,v3,v4,v5:
+ld4r { v2.4h, v3.4h, v4.4h, v5.4h }, [x2], x3
+v2,v3,v4,v5:
+ld4r { v2.8h, v3.8h, v4.8h, v5.8h }, [x2]
+v2,v3,v4,v5:
+ld4r { v2.8h, v3.8h, v4.8h, v5.8h }, [x2], x3
+v2,v3,v4,v5:
+ld4r { v2.2s, v3.2s, v4.2s, v5.2s }, [x2]
+v2,v3,v4,v5:
+ld4r { v2.2s, v3.2s, v4.2s, v5.2s }, [x2], x3
+v2,v3,v4,v5:
+ld4r { v2.4s, v3.4s, v4.4s, v5.4s }, [x2]
+v2,v3,v4,v5:
+ld4r { v2.4s, v3.4s, v4.4s, v5.4s }, [x2], x3
+v2,v3,v4,v5:
+ld4r { v2.1d, v3.1d, v4.1d, v5.1d }, [x2]
+v2,v3,v4,v5:
+ld4r { v2.1d, v3.1d, v4.1d, v5.1d }, [x2], x3
+v2,v3,v4,v5:
+ld4r { v2.2d, v3.2d, v4.2d, v5.2d }, [x2]
+v2,v3,v4,v5:
+ld4r { v2.2d, v3.2d, v4.2d, v5.2d }, [x2], x3
+v2,v3,v4,v5:
+ld4r { v2.8b, v3.8b, v4.8b, v5.8b }, [x2], #4
+v2,v3,v4,v5:
+ld4r { v2.16b, v3.16b, v4.16b, v5.16b }, [x2], #4
+v2,v3,v4,v5:
+ld4r { v2.4h, v3.4h, v4.4h, v5.4h }, [x2], #8
+v2,v3,v4,v5:
+ld4r { v2.8h, v3.8h, v4.8h, v5.8h }, [x2], #8
+v2,v3,v4,v5:
+ld4r { v2.2s, v3.2s, v4.2s, v5.2s }, [x2], #16
+v2,v3,v4,v5:
+ld4r { v2.4s, v3.4s, v4.4s, v5.4s }, [x2], #16
+v2,v3,v4,v5:
+ld4r { v2.1d, v3.1d, v4.1d, v5.1d }, [x2], #32
+v2,v3,v4,v5:
+ld4r { v2.2d, v3.2d, v4.2d, v5.2d }, [x2], #32
+v2,v3,v4,v5:
+ld1 { v6.b }[13], [x3]
+v6:
+ld1 { v6.h }[2], [x3]
+v6:
+ld1 { v6.s }[2], [x3]
+v6:
+ld1 { v6.d }[1], [x3]
+v6:
+ld1 { v6.b }[13], [x3], x5
+v6:
+ld1 { v6.h }[2], [x3], x5
+v6:
+ld1 { v6.s }[2], [x3], x5
+v6:
+ld1 { v6.d }[1], [x3], x5
+v6:
+ld1 { v6.b }[13], [x3], #1
+v6:
+ld1 { v6.h }[2], [x3], #2
+v6:
+ld1 { v6.s }[2], [x3], #4
+v6:
+ld1 { v6.d }[1], [x3], #8
+v6:
+ld2 { v5.b, v6.b }[13], [x3]
+v5,v6:
+ld2 { v5.h, v6.h }[2], [x3]
+v5,v6:
+ld2 { v5.s, v6.s }[2], [x3]
+v5,v6:
+ld2 { v5.d, v6.d }[1], [x3]
+v5,v6:
+ld2 { v5.b, v6.b }[13], [x3], x5
+v5,v6:
+ld2 { v5.h, v6.h }[2], [x3], x5
+v5,v6:
+ld2 { v5.s, v6.s }[2], [x3], x5
+v5,v6:
+ld2 { v5.d, v6.d }[1], [x3], x5
+v5,v6:
+ld2 { v5.b, v6.b }[13], [x3], #2
+v5,v6:
+ld2 { v5.h, v6.h }[2], [x3], #4
+v5,v6:
+ld2 { v5.s, v6.s }[2], [x3], #8
+v5,v6:
+ld2 { v5.d, v6.d }[1], [x3], #16
+v5,v6:
+ld3 { v7.b, v8.b, v9.b }[13], [x3]
+v7,v8,v9:
+ld3 { v7.h, v8.h, v9.h }[2], [x3]
+v7,v8,v9:
+ld3 { v7.s, v8.s, v9.s }[2], [x3]
+v7,v8,v9:
+ld3 { v7.d, v8.d, v9.d }[1], [x3]
+v7,v8,v9:
+ld3 { v7.b, v8.b, v9.b }[13], [x3], x5
+v7,v8,v9:
+ld3 { v7.h, v8.h, v9.h }[2], [x3], x5
+v7,v8,v9:
+ld3 { v7.s, v8.s, v9.s }[2], [x3], x5
+v7,v8,v9:
+ld3 { v7.d, v8.d, v9.d }[1], [x3], x5
+v7,v8,v9:
+ld3 { v7.b, v8.b, v9.b }[13], [x3], #3
+v7,v8,v9:
+ld3 { v7.h, v8.h, v9.h }[2], [x3], #6
+v7,v8,v9:
+ld3 { v7.s, v8.s, v9.s }[2], [x3], #12
+v7,v8,v9:
+ld3 { v7.d, v8.d, v9.d }[1], [x3], #24
+v7,v8,v9:
+ld4 { v7.b, v8.b, v9.b, v10.b }[13], [x3]
+v7,v8,v9,v10:
+ld4 { v7.h, v8.h, v9.h, v10.h }[2], [x3]
+v7,v8,v9,v10:
+ld4 { v7.s, v8.s, v9.s, v10.s }[2], [x3]
+v7,v8,v9,v10:
+ld4 { v7.d, v8.d, v9.d, v10.d }[1], [x3]
+v7,v8,v9,v10:
+ld4 { v7.b, v8.b, v9.b, v10.b }[13], [x3], x5
+v7,v8,v9,v10:
+ld4 { v7.h, v8.h, v9.h, v10.h }[2], [x3], x5
+v7,v8,v9,v10:
+ld4 { v7.s, v8.s, v9.s, v10.s }[2], [x3], x5
+v7,v8,v9,v10:
+ld4 { v7.d, v8.d, v9.d, v10.d }[1], [x3], x5
+v7,v8,v9,v10:
+ld4 { v7.b, v8.b, v9.b, v10.b }[13], [x3], #4
+v7,v8,v9,v10:
+ld4 { v7.h, v8.h, v9.h, v10.h }[2], [x3], #8
+v7,v8,v9,v10:
+ld4 { v7.s, v8.s, v9.s, v10.s }[2], [x3], #16
+v7,v8,v9,v10:
+ld4 { v7.d, v8.d, v9.d, v10.d }[1], [x3], #32
+v7,v8,v9,v10:
+
+@........................................................
+abs v0.8b , v0.8b 
+v0:
+abs v0.16b, v0.16b
+v0:
+abs v0.4h , v0.4h 
+v0:
+abs v0.8h , v0.8h 
+v0:
+abs v0.2s , v0.2s 
+v0:
+abs v0.4s , v0.4s 
+v0:
+add v0.8b , v0.8b , v0.8b 
+v0:
+add v0.16b, v0.16b, v0.16b
+v0:
+add v0.4h , v0.4h , v0.4h 
+v0:
+add v0.8h , v0.8h , v0.8h 
+v0:
+add v0.2s , v0.2s , v0.2s 
+v0:
+add v0.4s , v0.4s , v0.4s 
+v0:
+add v0.2d , v0.2d , v0.2d 
+v0:
+add d1, d2, d3
+d1:
+addhn   v0.8b , v0.8h,  v0.8h
+v0:
+addhn2  v0.16b, v0.8h,  v0.8h
+v0:
+addhn   v0.4h , v0.4s , v0.4s
+v0:
+addhn2  v0.8h , v0.4s , v0.4s
+v0:
+addhn   v0.2s , v0.2d , v0.2d
+v0:
+addhn2  v0.4s , v0.2d , v0.2d
+v0:
+addp    v0.8b , v0.8b , v0.8b 
+v0:
+addp    v0.16b, v0.16b, v0.16b
+v0:
+addp    v0.4h , v0.4h , v0.4h 
+v0:
+addp    v0.8h , v0.8h , v0.8h 
+v0:
+addp    v0.2s , v0.2s , v0.2s 
+v0:
+addp    v0.4s , v0.4s , v0.4s 
+v0:
+addp    v0.2d , v0.2d , v0.2d 
+v0:
+addp    d0, v0.2d 
+d0:
+addv    b0, v0.8b 
+b0:
+addv    b0, v0.16b
+b0:
+addv    h0, v0.4h 
+h0:
+addv    h0, v0.8h 
+h0:
+addv    s0, v0.4s 
+s0:
+
+dup v0.2d , x3
+v0:
+dup v0.4s , w3
+v0:
+dup v0.2s , w3
+v0:
+dup v0.8h , w3
+v0:
+dup v0.4h , w3
+v0:
+dup v0.16b, w3
+v0:
+dup v0.8b , w3
+v0:
+dup v1.2d, x3
+v1:
+dup v2.4s, w4
+v2:
+dup v3.2s, w5
+v3:
+dup v4.8h, w6
+v4:
+dup v5.4h, w7
+v5:
+dup v6.16b, w8
+v6:
+dup v7.8b, w9
+v7:
+dup v0.2d , v3.2d[1]
+v0:
+dup v0.2s , v3.2s[1]
+v0:
+dup v0.4s , v3.4s[1]
+v0:
+dup v0.4h , v3.4h[1]
+v0:
+dup v0.8h , v3.8h[1]
+v0:
+dup v0.8b , v3.8b[1]
+v0:
+dup v0.16b, v3.16b[1]
+v0:
+dup v7.2d, v9.d[1]
+v7:
+dup v6.2s, v8.s[1]
+v6:
+dup v5.4s, v7.s[2]
+v5:
+dup v4.4h, v6.h[3]
+v4:
+dup v3.8h, v5.h[4]
+v3:
+dup v2.8b, v4.b[5]
+v2:
+dup v1.16b, v3.b[6]
+v1:
+dup b3, v4.b[1]
+b3:
+dup h3, v4.h[1]
+h3:
+dup s3, v4.s[1]
+s3:
+dup d3, v4.d[1]
+d3:
+
+mov b3, v4.b[1]
+b3:
+mov h3, v4.h[1]
+h3:
+mov s3, v4.s[1]
+s3:
+mov d3, v4.d[1]
+d3:
+smov x3, v2.s[2]
+x3:
+umov w3, v2.s[2]
+w3:
+umov x3, v2.d[1]
+x3:
+
+@ MOV aliases for UMOV instructions above
+
+mov w5, v7.s[2]
+x5:
+mov x17, v19.d[0]
+x17:
+
+ins v2.d[1], x5
+v2:
+ins v2.s[1], w5
+v2:
+ins v2.h[1], w5
+v2:
+ins v2.b[1], w5
+v2:
+
+ins v2.d[1], v15.d[1]
+v2:
+ins v2.s[1], v15.s[1]
+v2:
+ins v2.h[1], v15.h[1]
+v2:
+ins v2.b[1], v15.b[1]
+v2:
+
+@ MOV aliases for the above INS instructions.
+
+mov v9.d[1], x2
+v9:
+mov v8.s[1], w3
+v8:
+mov v7.h[1], w4
+v7:
+mov v6.b[1], w5
+v6:
+mov v2.d[1], v15.d[0]
+v2:
+mov v7.s[3], v16.s[2]
+v7:
+mov v8.h[7], v17.h[3]
+v8:
+mov v9.b[10], v18.b[5]
+v9:
+and v0.8b, v0.8b, v0.8b
+v0:
+and v0.16b, v0.16b, v0.16b
+v0:
+bic v0.8b, v0.8b, v0.8b
+v0:
+cmeq v0.8b, v0.8b, v0.8b
+v0:
+cmge  v0.8b, v0.8b, v0.8b
+v0:
+cmgt  v0.8b, v0.8b, v0.8b
+v0:
+cmhi  v0.8b, v0.8b, v0.8b
+v0:
+cmhs  v0.8b, v0.8b, v0.8b
+v0:
+cmtst v0.8b, v0.8b, v0.8b
+v0:
+fabd v0.2s, v0.2s, v0.2s
+v0:
+facge v0.2s, v0.2s, v0.2s
+v0:
+facgt v0.2s, v0.2s, v0.2s
+v0:
+faddp v0.2s, v0.2s, v0.2s
+v0:
+fadd  v0.2s, v0.2s, v0.2s
+v0:
+fcmeq v0.2s, v0.2s, v0.2s
+v0:
+fcmge v0.2s, v0.2s, v0.2s
+v0:
+fcmgt v0.2s, v0.2s, v0.2s
+v0:
+fdiv  v0.2s, v0.2s, v0.2s
+v0:
+fmaxnmp v0.2s, v0.2s, v0.2s
+v0:
+fmaxnm  v0.2s, v0.2s, v0.2s
+v0:
+fmaxp   v0.2s, v0.2s, v0.2s
+v0:
+fmax v0.2s, v0.2s, v0.2s
+v0:
+fminnmp v0.2s, v0.2s, v0.2s
+v0:
+fminnm v0.2s, v0.2s, v0.2s
+v0:
+fminp v0.2s, v0.2s, v0.2s
+v0:
+fmin v0.2s, v0.2s, v0.2s
+v0:
+fmla v0.2s, v0.2s, v0.2s
+v0:
+fmls v0.2s, v0.2s, v0.2s
+v0:
+fmulx v0.2s, v0.2s, v0.2s
+v0:
+fmul v0.2s, v0.2s, v0.2s
+v0:
+frecps v0.2s, v0.2s, v0.2s
+v0:
+frsqrts v0.2s, v0.2s, v0.2s
+v0:
+fsub    v0.2s, v0.2s, v0.2s
+v0:
+mla     v0.8b, v0.8b, v0.8b
+v0:
+mls     v0.8b, v0.8b, v0.8b
+v0:
+mul     v0.8b, v0.8b, v0.8b
+v0:
+pmul    v0.8b, v0.8b, v0.8b
+v0:
+saba    v0.8b, v0.8b, v0.8b
+v0:
+sabd    v0.8b, v0.8b, v0.8b
+v0:
+shadd   v0.8b, v0.8b, v0.8b
+v0:
+shsub   v0.8b, v0.8b, v0.8b
+v0:
+smaxp   v0.8b, v0.8b, v0.8b
+v0:
+smax    v0.8b, v0.8b, v0.8b
+v0:
+sminp   v0.8b, v0.8b, v0.8b
+v0:
+smin    v0.8b, v0.8b, v0.8b
+v0:
+sqadd   v0.8b, v0.8b, v0.8b
+v0:
+sqdmulh  v0.4h, v0.4h, v0.4h
+v0:
+sqrdmulh v0.4h, v0.4h, v0.4h
+v0:
+sqrshl   v0.8b, v0.8b, v0.8b
+v0:
+sqshl    v0.8b, v0.8b, v0.8b
+v0:
+sqsub    v0.8b, v0.8b, v0.8b
+v0:
+srhadd   v0.8b, v0.8b, v0.8b
+v0:
+srshl    v0.8b, v0.8b, v0.8b
+v0:
+
+sshl v0.8b, v0.8b, v0.8b
+v0:
+sub v0.8b, v0.8b, v0.8b
+v0:
+uaba v0.8b, v0.8b, v0.8b
+v0:
+uabd v0.8b, v0.8b, v0.8b
+v0:
+uhadd v0.8b, v0.8b, v0.8b
+v0:
+uhsub v0.8b, v0.8b, v0.8b
+v0:
+umaxp v0.8b, v0.8b, v0.8b
+v0:
+umax v0.8b, v0.8b, v0.8b
+v0:
+uminp v0.8b, v0.8b, v0.8b
+v0:
+umin   v0.8b,  v0.8b,  v0.8b
+v0:
+uqadd   v0.8b,  v0.8b,  v0.8b
+v0:
+uqrshl   v0.8b,  v0.8b,  v0.8b
+v0:
+uqshl   v0.8b,  v0.8b,  v0.8b
+v0:
+uqsub   v0.8b,  v0.8b,  v0.8b
+v0:
+urhadd   v0.8b,  v0.8b,  v0.8b
+v0:
+urshl   v0.8b,  v0.8b,  v0.8b
+v0:
+ushl   v0.8b,  v0.8b,  v0.8b
+v0:
+bif   v0.8b,  v0.8b,  v0.8b
+v0:
+bit   v0.8b,  v0.8b,  v0.8b
+v0:
+bsl   v0.8b,  v0.8b,  v0.8b
+v0:
+eor   v0.8b,  v0.8b,  v0.8b
+v0:
+orn   v0.8b,  v0.8b,  v0.8b
+v0:
+orr v0.8b, v0.8b, v1.8b
+v0:
+
+sadalp v0.4h, v0.8b
+v0:
+sadalp v0.8h, v0.16b
+v0:
+sadalp v0.2s, v0.4h
+v0:
+sadalp v0.4s, v0.8h
+v0:
+sadalp v0.1d, v0.2s
+v0:
+sadalp v0.2d, v0.4s
+v0:
+
+
+cls v0.8b, v0.8b
+v0:
+clz v0.8b, v0.8b
+v0:
+cnt v0.8b, v0.8b
+v0:
+fabs   v0.2s, v0.2s
+v0:
+fneg   v0.2s, v0.2s
+v0:
+frecpe v0.2s, v0.2s
+v0:
+frinta v0.2s, v0.2s
+v0:
+frintx v0.2s, v0.2s
+v0:
+frinti v0.2s, v0.2s
+v0:
+frintm v0.2s, v0.2s
+v0:
+frintn v0.2s, v0.2s
+v0:
+frintp v0.2s, v0.2s
+v0:
+frintz v0.2s, v0.2s
+v0:
+frsqrte v0.2s, v0.2s
+v0:
+fsqrt   v0.2s, v0.2s
+v0:
+
+neg   v0.8b, v0.8b
+v0:
+not   v0.8b, v0.8b
+v0:
+rbit   v0.8b, v0.8b
+v0:
+rev16   v0.8b, v0.8b
+v0:
+rev32   v0.8b, v0.8b
+v0:
+rev64   v0.8b, v0.8b
+v0:
+scvtf v0.2s, v0.2s
+v0:
+sqabs v0.8b, v0.8b
+v0:
+sqneg v0.8b, v0.8b
+v0:
+sqxtn v0.8b, v0.8h
+v0:
+sqxtun v0.8b, v0.8h
+v0:
+suqadd v0.8b, v0.8b
+v0:
+uadalp v0.4h, v0.8b
+v0:
+uaddlp v0.4h, v0.8b
+v0:
+ucvtf   v0.2s, v0.2s
+v0:
+uqxtn   v0.8b, v0.8h
+v0:
+urecpe  v0.2s, v0.2s
+v0:
+ursqrte v0.2s, v0.2s
+v0:
+usqadd  v0.8b, v0.8b
+v0:
+
+shll v1.8h, v2.8b, #8
+v1:
+shll v1.4s, v2.4h, #16
+v1:
+shll v1.2d, v2.2s, #32
+v1:
+shll2 v1.8h, v2.16b, #8
+v1:
+shll2 v1.4s, v2.8h, #16
+v1:
+shll2 v1.2d, v2.4s, #32
+v1:
+
+cmeq v0.8b , v0.8b , #0
+v0:
+cmeq v0.16b, v0.16b, #0
+v0:
+cmeq v0.4h , v0.4h , #0
+v0:
+cmeq v0.8h , v0.8h , #0
+v0:
+cmeq v0.2s , v0.2s , #0
+v0:
+cmeq v0.4s , v0.4s , #0
+v0:
+cmeq v0.2d , v0.2d , #0
+v0:
+cmge v0.8b , v0.8b , #0
+v0:
+cmgt v0.8b , v0.8b , #0
+v0:
+cmle v0.8b , v0.8b , #0
+v0:
+
+
+fcmeq v0.2s, v0.2s, #0
+v0:
+fcmge v0.2s, v0.2s, #0
+v0:
+fcmgt v0.2s, v0.2s, #0
+v0:
+fcmle v0.2s, v0.2s, #0
+v0:
+fcmlt v0.2s, v0.2s, #0
+v0:
+
+cmlt v8.8b, v14.8b, #0
+v8:
+cmlt v8.16b, v14.16b, #0
+v8:
+cmlt v8.4h, v14.4h, #0
+v8:
+cmlt v8.8h, v14.8h, #0
+v8:
+cmlt v8.2s, v14.2s, #0
+v8:
+cmlt v8.4s, v14.4s, #0
+v8:
+cmlt v8.2d, v14.2d, #0
+v8:
+@===-------------------------------------------------------------------------===
+@ AdvSIMD Floating-point <-> Integer Conversions
+@===-------------------------------------------------------------------------===
+fcvtas v0.2s, v0.2s
+v0:
+fcvtas v0.4s, v0.4s
+v0:
+fcvtas v0.2d, v0.2d
+v0:
+fcvtas s0, s0
+s0:
+fcvtas d0, d0
+d0:
+fcvtau v0.2s, v0.2s
+v0:
+fcvtau v0.4s, v0.4s
+v0:
+fcvtau v0.2d, v0.2d
+v0:
+fcvtau s0, s0
+s0:
+fcvtau d0, d0
+d0:
+fcvtl v1.4s, v5.4h
+v1:
+fcvtl v2.2d, v6.2s
+v2:
+fcvtl2 v3.4s, v7.8h
+v3:
+fcvtl2 v4.2d, v8.4s
+v4:
+fcvtms v0.2s, v0.2s
+v0:
+fcvtms v0.4s, v0.4s
+v0:
+fcvtms v0.2d, v0.2d
+v0:
+fcvtms s0, s0
+s0:
+fcvtms d0, d0
+d0:
+fcvtmu v0.2s, v0.2s
+v0:
+fcvtmu v0.4s, v0.4s
+v0:
+fcvtmu v0.2d, v0.2d
+v0:
+fcvtmu s0, s0
+s0:
+fcvtmu d0, d0
+d0:
+fcvtns v0.2s, v0.2s
+v0:
+fcvtns v0.4s, v0.4s
+v0:
+fcvtns v0.2d, v0.2d
+v0:
+fcvtns s0, s0
+s0:
+fcvtns d0, d0
+d0:
+fcvtnu v0.2s, v0.2s
+v0:
+fcvtnu v0.4s, v0.4s
+v0:
+fcvtnu v0.2d, v0.2d
+v0:
+fcvtnu s0, s0
+s0:
+fcvtnu d0, d0
+d0:
+fcvtn v2.4h, v4.4s
+v2:
+fcvtn v3.2s, v5.2d
+v3:
+fcvtn2 v4.8h, v6.4s
+v4:
+fcvtn2 v5.4s, v7.2d
+v5:
+fcvtxn v6.2s, v9.2d
+v6:
+fcvtxn2 v7.4s, v8.2d
+v7:
+fcvtps v0.2s, v0.2s
+v0:
+fcvtps v0.4s, v0.4s
+v0:
+fcvtps v0.2d, v0.2d
+v0:
+fcvtps s0, s0
+s0:
+fcvtps d0, d0
+d0:
+fcvtpu v0.2s, v0.2s
+v0:
+fcvtpu v0.4s, v0.4s
+v0:
+fcvtpu v0.2d, v0.2d
+v0:
+fcvtpu s0, s0
+s0:
+fcvtpu d0, d0
+d0:
+fcvtzs v0.2s, v0.2s
+v0:
+fcvtzs v0.4s, v0.4s
+v0:
+fcvtzs v0.2d, v0.2d
+v0:
+fcvtzs s0, s0
+s0:
+fcvtzs d0, d0
+d0:
+fcvtzu v0.2s, v0.2s
+v0:
+fcvtzu v0.4s, v0.4s
+v0:
+fcvtzu v0.2d, v0.2d
+v0:
+fcvtzu s0, s0
+s0:
+fcvtzu d0, d0
+d0:
+@===-------------------------------------------------------------------------===
+@ AdvSIMD modified immediate instructions
+@===-------------------------------------------------------------------------===
+bic v0.2s, #1
+v0:
+bic v0.2s, #1, lsl #0
+v0:
+bic v0.2s, #1, lsl #8
+v0:
+bic v0.2s, #1, lsl #16
+v0:
+bic v0.2s, #1, lsl #24
+v0:
+bic v0.4h, #1
+v0:
+bic v0.4h, #1, lsl #0
+v0:
+bic v0.4h, #1, lsl #8
+v0:
+bic v0.4s, #1
+v0:
+bic v0.4s, #1, lsl #0
+v0:
+bic v0.4s, #1, lsl #8
+v0:
+bic v0.4s, #1, lsl #16
+v0:
+bic v0.4s, #1, lsl #24
+v0:
+bic v0.8h, #1
+v0:
+bic v0.8h, #1, lsl #0
+v0:
+bic v0.8h, #1, lsl #8
+v0:
+fmov v0.2d, #1.250000e-01
+v0:
+fmov v0.2s, #1.250000e-01
+v0:
+fmov v0.4s, #1.250000e-01
+v0:
+orr v0.2s, #1
+v0:
+orr v0.2s, #1, lsl #0
+v0:
+orr v0.2s, #1, lsl #8
+v0:
+orr v0.2s, #1, lsl #16
+v0:
+orr v0.2s, #1, lsl #24
+v0:
+orr v0.4h, #1
+v0:
+orr v0.4h, #1, lsl #0
+v0:
+orr v0.4h, #1, lsl #8
+v0:
+orr v0.4s, #1
+v0:
+orr v0.4s, #1, lsl #0
+v0:
+orr v0.4s, #1, lsl #8
+v0:
+orr v0.4s, #1, lsl #16
+v0:
+orr v0.4s, #1, lsl #24
+v0:
+orr v0.8h, #1
+v0:
+orr v0.8h, #1, lsl #0
+v0:
+orr v0.8h, #1, lsl #8
+v0:
+
+
+
+movi d0, #0x000000000000ff
+d0:
+movi v0.2d, #0x000000000000ff
+v0:
+
+movi v0.2s, #1
+v0:
+movi v0.2s, #1, lsl #0
+v0:
+movi v0.2s, #1, lsl #8
+v0:
+movi v0.2s, #1, lsl #16
+v0:
+movi v0.2s, #1, lsl #24
+v0:
+movi v0.4s, #1
+v0:
+movi v0.4s, #1, lsl #0
+v0:
+movi v0.4s, #1, lsl #8
+v0:
+movi v0.4s, #1, lsl #16
+v0:
+movi v0.4s, #1, lsl #24
+v0:
+movi v0.4h, #1
+v0:
+movi v0.4h, #1, lsl #0
+v0:
+movi v0.4h, #1, lsl #8
+v0:
+movi v0.8h, #1
+v0:
+movi v0.8h, #1, lsl #0
+v0:
+movi v0.8h, #1, lsl #8
+v0:
+movi v0.2s, #1, msl #8
+v0:
+movi v0.2s, #1, msl #16
+v0:
+movi v0.4s, #1, msl #8
+v0:
+movi v0.4s, #1, msl #16
+v0:
+movi v0.8b, #1
+v0:
+movi v0.16b, #1
+v0:
+mvni v0.2s, #1
+v0:
+mvni v0.2s, #1, lsl #0
+v0:
+mvni v0.2s, #1, lsl #8
+v0:
+mvni v0.2s, #1, lsl #16
+v0:
+mvni v0.2s, #1, lsl #24
+v0:
+mvni v0.4s, #1
+v0:
+mvni v0.4s, #1, lsl #0
+v0:
+mvni v0.4s, #1, lsl #8
+v0:
+mvni v0.4s, #1, lsl #16
+v0:
+mvni v0.4s, #1, lsl #24
+v0:
+mvni v0.4h, #1
+v0:
+mvni v0.4h, #1, lsl #0
+v0:
+mvni v0.4h, #1, lsl #8
+v0:
+mvni v0.8h, #1
+v0:
+mvni v0.8h, #1, lsl #0
+v0:
+mvni v0.8h, #1, lsl #8
+v0:
+mvni v0.2s, #1, msl #8
+v0:
+mvni v0.2s, #1, msl #16
+v0:
+mvni v0.4s, #1, msl #8
+v0:
+mvni v0.4s, #1, msl #16
+v0:
+
+@===-------------------------------------------------------------------------===
+@ AdvSIMD scalar x index
+@===-------------------------------------------------------------------------===
+
+fmla s0, s0, v0.s[3]
+s0:
+fmla d0, d0, v0.d[1]
+d0:
+
+fmls s0, s0, v0.s[3]
+s0:
+fmls d0, d0, v0.d[1]
+d0:
+fmulx s0, s0, v0.s[3]
+s0:
+fmulx d0, d0, v0.d[1]
+d0:
+fmul  s0, s0, v0.s[3]
+s0:
+fmul  d0, d0, v0.d[1]
+d0:
+sqdmlal s0, h0, v0.h[7]
+s0:
+sqdmlal d0, s0, v0.s[3]
+d0:
+sqdmlsl s0, h0, v0.h[7]
+s0:
+sqdmulh h0, h0, v0.h[7]
+h0:
+sqdmulh s0, s0, v0.s[3]
+s0:
+sqdmull s0, h0, v0.h[7]
+s0:
+sqdmull d0, s0, v0.s[3]
+d0:
+sqrdmulh h0, h0, v0.h[7]
+h0:
+sqrdmulh s0, s0, v0.s[3]
+s0:
+
+@===-------------------------------------------------------------------------===
+@ AdvSIMD SMLAL
+@===-------------------------------------------------------------------------===
+
+smlal v13.8h, v8.8b, v0.8b
+v13:
+smlal v13.4s, v8.4h, v0.4h
+v13:
+smlal v13.2d, v8.2s, v0.2s
+v13:
+smlal2 v13.8h, v8.16b, v0.16b
+v13:
+smlal2 v13.4s, v8.8h, v0.8h
+v13:
+smlal2 v13.2d, v8.4s, v0.4s
+v13:
+@===-------------------------------------------------------------------------===
+@ AdvSIMD scalar x index
+@===-------------------------------------------------------------------------===
+fmla v0.2s, v0.2s, v0.2s[0]
+v0:
+fmla v0.4s, v0.4s, v0.4s[1]
+v0:
+fmla v0.2d, v0.2d, v0.2d[1]
+v0:
+fmls v0.2s, v0.2s, v0.2s[0]
+v0:
+fmls v0.4s, v0.4s, v0.4s[1]
+v0:
+fmls v0.2d, v0.2d, v0.2d[1]
+v0:
+fmulx v0.2s, v0.2s, v0.2s[0]
+v0:
+fmulx v0.4s, v0.4s, v0.4s[1]
+v0:
+fmulx v0.2d, v0.2d, v0.2d[1]
+v0:
+fmul  v0.2s, v0.2s, v0.2s[0]
+v0:
+fmul  v0.4s, v0.4s, v0.4s[1]
+v0:
+fmul  v0.2d, v0.2d, v0.2d[1]
+v0:
+mla v0.4h, v0.4h, v0.4h[0]
+v0:
+mla v0.8h, v0.8h, v0.8h[1]
+v0:
+mla v0.2s, v0.2s, v0.2s[2]
+v0:
+mla v0.4s, v0.4s, v0.4s[3]
+v0:
+mls v0.4h, v0.4h, v0.4h[0]
+v0:
+mls v0.8h, v0.8h, v0.8h[1]
+v0:
+mls v0.2s, v0.2s, v0.2s[2]
+v0:
+mls v0.4s, v0.4s, v0.4s[3]
+v0:
+mul v0.4h, v0.4h, v0.4h[0]
+v0:
+mul v0.8h, v0.8h, v0.8h[1]
+v0:
+mul v0.2s, v0.2s, v0.2s[2]
+v0:
+mul v0.4s, v0.4s, v0.4s[3]
+v0:
+smlal  v0.4s, v0.4h, v0.h[0]
+v0:
+smlal2 v0.4s, v0.8h, v0.h[1]
+v0:
+smlal  v0.2d, v0.2s, v0.s[2]
+v0:
+smlal2 v0.2d, v0.4s, v0.s[3]
+v0:
+smlsl  v0.4s, v0.4h, v0.h[0]
+v0:
+smlsl2 v0.4s, v0.8h, v0.h[1]
+v0:
+smlsl  v0.2d, v0.2s, v0.s[2]
+v0:
+smlsl2 v0.2d, v0.4s, v0.s[3]
+v0:
+smull  v0.4s, v0.4h, v0.h[0]
+v0:
+smull2 v0.4s, v0.8h, v0.h[1]
+v0:
+smull  v0.2d, v0.2s, v0.s[2]
+v0:
+smull2 v0.2d, v0.4s, v0.s[3]
+v0:
+sqdmlal  v0.4s, v0.4h, v0.h[0]
+v0:
+sqdmlal2 v0.4s, v0.8h, v0.h[1]
+v0:
+sqdmlal  v0.2d, v0.2s, v0.s[2]
+v0:
+sqdmlal2 v0.2d, v0.4s, v0.s[3]
+v0:
+sqdmlsl  v0.4s, v0.4h, v0.h[0]
+v0:
+sqdmlsl2 v0.4s, v0.8h, v0.h[1]
+v0:
+sqdmlsl  v0.2d, v0.2s, v0.s[2]
+v0:
+sqdmlsl2 v0.2d, v0.4s, v0.s[3]
+v0:
+sqdmull  v0.2d, v0.2s, v0.s[2]
+v0:
+sqdmull2 v0.2d, v0.4s, v0.s[3]
+v0:
+sqrdmulh v0.4h, v0.4h, v0.h[0]
+v0:
+sqrdmulh v0.8h, v0.8h, v0.h[1]
+v0:
+sqrdmulh v0.2s, v0.2s, v0.s[2]
+v0:
+sqrdmulh v0.4s, v0.4s, v0.s[3]
+v0:
+umlal  v0.4s, v0.4h, v0.h[0]
+v0:
+umlal2 v0.4s, v0.8h, v0.h[1]
+v0:
+umlal  v0.2d, v0.2s, v0.s[2]
+v0:
+umlal2 v0.2d, v0.4s, v0.s[3]
+v0:
+umlsl  v0.4s, v0.4h, v0.h[0]
+v0:
+umlsl2 v0.4s, v0.8h, v0.h[1]
+v0:
+umlsl  v0.2d, v0.2s, v0.s[2]
+v0:
+umlsl2 v0.2d, v0.4s, v0.s[3]
+v0:
+umull  v0.4s, v0.4h, v0.h[0]
+v0:
+umull2 v0.4s, v0.8h, v0.h[1]
+v0:
+umull  v0.2d, v0.2s, v0.s[2]
+v0:
+umull2 v0.2d, v0.4s, v0.s[3]
+v0:
+@===-------------------------------------------------------------------------===
+@ AdvSIMD scalar with shift
+@===-------------------------------------------------------------------------===
+fcvtzs s0, s0, #1
+s0:
+fcvtzs d0, d0, #2
+d0:
+fcvtzu s0, s0, #1
+s0:
+fcvtzu d0, d0, #2
+d0:
+shl d0, d0, #1
+d0:
+sli d0, d0, #1
+d0:
+sqrshrn b0, h0, #1
+b0:
+sqrshrn h0, s0, #2
+h0:
+sqrshrn s0, d0, #3
+s0:
+sqrshrun b0, h0, #1
+b0:
+sqrshrun h0, s0, #2
+h0:
+sqrshrun s0, d0, #3
+s0:
+sqshlu b0, b0, #1
+b0:
+sqshlu h0, h0, #2
+h0:
+sqshlu s0, s0, #3
+s0:
+sqshlu d0, d0, #4
+d0:
+sqshl b0, b0, #1
+b0:
+sqshl h0, h0, #2
+h0:
+sqshl s0, s0, #3
+s0:
+sqshl d0, d0, #4
+d0:
+sqshrn b0, h0, #1
+b0:
+sqshrn h0, s0, #2
+h0:
+sqshrn s0, d0, #3
+s0:
+sqshrun b0, h0, #1
+b0:
+sqshrun h0, s0, #2
+h0:
+sqshrun s0, d0, #3
+s0:
+sri d0, d0, #1
+d0:
+srshr d0, d0, #1
+d0:
+srsra d0, d0, #1
+d0:
+sshr d0, d0, #1
+d0:
+ucvtf s0, s0, #1
+s0:
+ucvtf d0, d0, #2
+d0:
+scvtf s0, s0, #1
+s0:
+scvtf d0, d0, #2
+d0:
+uqrshrn b0, h0, #1
+b0:
+uqrshrn h0, s0, #2
+h0:
+uqrshrn s0, d0, #3
+s0:
+uqshl b0, b0, #1
+b0:
+uqshl h0, h0, #2
+h0:
+uqshl s0, s0, #3
+s0:
+uqshl d0, d0, #4
+d0:
+uqshrn b0, h0, #1
+b0:
+uqshrn h0, s0, #2
+h0:
+uqshrn s0, d0, #3
+s0:
+urshr d0, d0, #1
+d0:
+ursra d0, d0, #1
+d0:
+ushr d0, d0, #1
+d0:
+usra d0, d0, #1
+d0:
+
+@===-------------------------------------------------------------------------===
+@ AdvSIMD vector with shift
+@===-------------------------------------------------------------------------===
+fcvtzs v0.2s , v0.2s , #1
+v0:
+fcvtzs v0.4s , v0.4s , #2
+v0:
+fcvtzs v0.2d , v0.2d , #3
+v0:
+fcvtzu v0.2s , v0.2s , #1
+v0:
+fcvtzu v0.4s , v0.4s , #2
+v0:
+fcvtzu v0.2d , v0.2d , #3
+v0:
+rshrn  v0.8b , v0.8h , #1
+v0:
+rshrn2 v0.16b, v0.8h, #2
+v0:
+rshrn  v0.4h , v0.4s , #3
+v0:
+rshrn2 v0.8h , v0.4s , #4
+v0:
+rshrn  v0.2s , v0.2d , #5
+v0:
+rshrn2 v0.4s , v0.2d , #6
+v0:
+scvtf  v0.2s , v0.2s , #1
+v0:
+scvtf  v0.4s , v0.4s , #2
+v0:
+scvtf  v0.2d , v0.2d , #3
+v0:
+shl    v0.8b , v0.8b , #1
+v0:
+shl    v0.16b, v0.16b, #2
+v0:
+shl    v0.4h , v0.4h , #3
+v0:
+shl    v0.8h , v0.8h , #4
+v0:
+shl    v0.2s , v0.2s , #5
+v0:
+shl    v0.4s , v0.4s , #6
+v0:
+shl    v0.2d , v0.2d , #7
+v0:
+shrn   v0.8b , v0.8h , #1
+v0:
+shrn2  v0.16b, v0.8h, #2
+v0:
+shrn   v0.4h , v0.4s , #3
+v0:
+shrn2  v0.8h , v0.4s , #4
+v0:
+shrn   v0.2s , v0.2d , #5
+v0:
+shrn2  v0.4s , v0.2d , #6
+v0:
+sli    v0.8b , v0.8b , #1
+v0:
+sli    v0.16b, v0.16b, #2
+v0:
+sli    v0.4h , v0.4h , #3
+v0:
+sli    v0.8h , v0.8h , #4
+v0:
+sli    v0.2s , v0.2s , #5
+v0:
+sli    v0.4s , v0.4s , #6
+v0:
+sli    v0.2d , v0.2d , #7
+v0:
+sqrshrn   v0.8b , v0.8h , #1
+v0:
+sqrshrn2  v0.16b, v0.8h, #2
+v0:
+sqrshrn   v0.4h , v0.4s , #3
+v0:
+sqrshrn2  v0.8h , v0.4s , #4
+v0:
+sqrshrn   v0.2s , v0.2d , #5
+v0:
+sqrshrn2  v0.4s , v0.2d , #6
+v0:
+sqrshrun  v0.8b , v0.8h , #1
+v0:
+sqrshrun2 v0.16b, v0.8h, #2
+v0:
+sqrshrun  v0.4h , v0.4s , #3
+v0:
+sqrshrun2 v0.8h , v0.4s , #4
+v0:
+sqrshrun  v0.2s , v0.2d , #5
+v0:
+sqrshrun2 v0.4s , v0.2d , #6
+v0:
+sqshlu    v0.8b , v0.8b , #1
+v0:
+sqshlu    v0.16b, v0.16b, #2
+v0:
+sqshlu    v0.4h , v0.4h , #3
+v0:
+sqshlu    v0.8h , v0.8h , #4
+v0:
+sqshlu    v0.2s , v0.2s , #5
+v0:
+sqshlu    v0.4s , v0.4s , #6
+v0:
+sqshlu    v0.2d , v0.2d , #7
+v0:
+sqshl     v0.8b , v0.8b , #1
+v0:
+sqshl     v0.16b, v0.16b, #2
+v0:
+sqshl     v0.4h , v0.4h , #3
+v0:
+sqshl     v0.8h , v0.8h , #4
+v0:
+sqshl     v0.2s , v0.2s , #5
+v0:
+sqshl     v0.4s , v0.4s , #6
+v0:
+sqshl     v0.2d , v0.2d , #7
+v0:
+sqshrn    v0.8b , v0.8h , #1
+v0:
+sqshrn2   v0.16b, v0.8h, #2
+v0:
+sqshrn    v0.4h , v0.4s , #3
+v0:
+sqshrn2   v0.8h , v0.4s , #4
+v0:
+sqshrn    v0.2s , v0.2d , #5
+v0:
+sqshrn2   v0.4s , v0.2d , #6
+v0:
+sqshrun   v0.8b , v0.8h , #1
+v0:
+sqshrun2  v0.16b, v0.8h, #2
+v0:
+sqshrun   v0.4h , v0.4s , #3
+v0:
+sqshrun2  v0.8h , v0.4s , #4
+v0:
+sqshrun   v0.2s , v0.2d , #5
+v0:
+sqshrun2  v0.4s , v0.2d , #6
+v0:
+sri       v0.8b , v0.8b , #1
+v0:
+sri       v0.16b, v0.16b, #2
+v0:
+sri       v0.4h , v0.4h , #3
+v0:
+sri       v0.8h , v0.8h , #4
+v0:
+sri       v0.2s , v0.2s , #5
+v0:
+sri       v0.4s , v0.4s , #6
+v0:
+sri       v0.2d , v0.2d , #7
+v0:
+srshr     v0.8b , v0.8b , #1
+v0:
+srshr     v0.16b, v0.16b, #2
+v0:
+srshr     v0.4h , v0.4h , #3
+v0:
+srshr     v0.8h , v0.8h , #4
+v0:
+srshr     v0.2s , v0.2s , #5
+v0:
+srshr     v0.4s , v0.4s , #6
+v0:
+srshr     v0.2d , v0.2d , #7
+v0:
+srsra     v0.8b , v0.8b , #1
+v0:
+srsra     v0.16b, v0.16b, #2
+v0:
+srsra     v0.4h , v0.4h , #3
+v0:
+srsra     v0.8h , v0.8h , #4
+v0:
+srsra     v0.2s , v0.2s , #5
+v0:
+srsra     v0.4s , v0.4s , #6
+v0:
+srsra     v0.2d , v0.2d , #7
+v0:
+sshll     v0.8h , v0.8b , #1
+v0:
+sshll2    v0.8h , v0.16b, #2
+v0:
+sshll     v0.4s , v0.4h , #3
+v0:
+sshll2    v0.4s , v0.8h , #4
+v0:
+sshll     v0.2d , v0.2s , #5
+v0:
+sshll2    v0.2d , v0.4s , #6
+v0:
+sshr  v0.8b , v0.8b , #1
+v0:
+sshr  v0.16b, v0.16b, #2
+v0:
+sshr  v0.4h , v0.4h , #3
+v0:
+sshr  v0.8h , v0.8h , #4
+v0:
+sshr  v0.2s , v0.2s , #5
+v0:
+sshr  v0.4s , v0.4s , #6
+v0:
+sshr  v0.2d , v0.2d , #7
+v0:
+sshr  v0.8b , v0.8b , #1
+v0:
+ssra  v0.16b, v0.16b, #2
+v0:
+ssra  v0.4h , v0.4h , #3
+v0:
+ssra  v0.8h , v0.8h , #4
+v0:
+ssra  v0.2s , v0.2s , #5
+v0:
+ssra  v0.4s , v0.4s , #6
+v0:
+ssra  v0.2d , v0.2d , #7
+v0:
+ssra d0, d0, #64
+v0:
+ucvtf       v0.2s , v0.2s , #1
+v0:
+ucvtf       v0.4s , v0.4s , #2
+v0:
+ucvtf       v0.2d , v0.2d , #3
+v0:
+uqrshrn     v0.8b , v0.8h , #1
+v0:
+uqrshrn2    v0.16b, v0.8h, #2
+v0:
+uqrshrn     v0.4h , v0.4s , #3
+v0:
+uqrshrn2    v0.8h , v0.4s , #4
+v0:
+uqrshrn     v0.2s , v0.2d , #5
+v0:
+uqrshrn2    v0.4s , v0.2d , #6
+v0:
+uqshl       v0.8b , v0.8b , #1
+v0:
+uqshl       v0.16b, v0.16b, #2
+v0:
+uqshl       v0.4h , v0.4h , #3
+v0:
+uqshl       v0.8h , v0.8h , #4
+v0:
+uqshl       v0.2s , v0.2s , #5
+v0:
+uqshl       v0.4s , v0.4s , #6
+v0:
+uqshl       v0.2d , v0.2d , #7
+v0:
+uqshrn      v0.8b , v0.8h , #1
+v0:
+uqshrn2     v0.16b, v0.8h, #2
+v0:
+uqshrn      v0.4h , v0.4s , #3
+v0:
+uqshrn2     v0.8h , v0.4s , #4
+v0:
+uqshrn      v0.2s , v0.2d , #5
+v0:
+uqshrn2     v0.4s , v0.2d , #6
+v0:
+urshr       v0.8b , v0.8b , #1
+v0:
+urshr       v0.16b, v0.16b, #2
+v0:
+urshr       v0.4h , v0.4h , #3
+v0:
+urshr       v0.8h , v0.8h , #4
+v0:
+urshr       v0.2s , v0.2s , #5
+v0:
+urshr       v0.4s , v0.4s , #6
+v0:
+urshr       v0.2d , v0.2d , #7
+v0:
+ursra   v0.8b , v0.8b , #1
+v0:
+ursra   v0.16b, v0.16b, #2
+v0:
+ursra   v0.4h , v0.4h , #3
+v0:
+ursra   v0.8h , v0.8h , #4
+v0:
+ursra   v0.2s , v0.2s , #5
+v0:
+ursra   v0.4s , v0.4s , #6
+v0:
+ursra   v0.2d , v0.2d , #7
+v0:
+ushll   v0.8h , v0.8b , #1
+v0:
+ushll2  v0.8h , v0.16b , #2
+v0:
+ushll   v0.4s , v0.4h , #3
+v0:
+ushll2  v0.4s , v0.8h , #4
+v0:
+ushll   v0.2d , v0.2s , #5
+v0:
+ushll2  v0.2d , v0.4s , #6
+v0:
+ushr    v0.8b , v0.8b , #1
+v0:
+ushr    v0.16b, v0.16b, #2
+v0:
+ushr    v0.4h , v0.4h , #3
+v0:
+ushr    v0.8h , v0.8h , #4
+v0:
+ushr    v0.2s , v0.2s , #5
+v0:
+ushr    v0.4s , v0.4s , #6
+v0:
+ushr    v0.2d , v0.2d , #7
+v0:
+usra    v0.8b , v0.8b , #1
+v0:
+usra    v0.16b, v0.16b, #2
+v0:
+usra    v0.4h , v0.4h , #3
+v0:
+usra    v0.8h , v0.8h , #4
+v0:
+usra    v0.2s , v0.2s , #5
+v0:
+usra    v0.4s , v0.4s , #6
+v0:
+usra    v0.2d , v0.2d , #7
+v0:
+sqdmull  v10.4s, v12.4h, v12.4h
+v10:
+sqdmull2 v10.4s, v13.8h, v13.8h
+v10:
+sqdmull  v10.2d, v13.2s, v13.2s
+v10:
+sqdmull2 v10.2d, v13.4s, v13.4s
+v10:
+xtn  v14.8b, v14.8h
+v14:
+xtn2 v14.16b, v14.8h
+v14:
+xtn  v14.4h, v14.4s
+v14:
+xtn2 v14.8h, v14.4s
+v14:
+xtn  v14.2s, v14.2d
+v14:
+xtn2 v14.4s, v14.2d
+v14:
+uaddl  v9.8h, v13.8b, v14.8b
+v9:
+uaddl2 v9.8h, v13.16b, v14.16b
+v9:
+uaddl  v9.4s, v13.4h, v14.4h
+v9:
+uaddl2 v9.4s, v13.8h, v14.8h
+v9:
+uaddl  v9.2d, v13.2s, v14.2s
+v9:
+uaddl2 v9.2d, v13.4s, v14.4s
+v9:
+bit v9.16b, v10.16b, v10.16b
+v9:
+bit v9.8b, v10.8b, v10.8b
+v9:
+pmull  v8.8h, v8.8b, v8.8b
+v8:
+pmull2 v8.8h, v8.16b, v8.16b
+v8:
+usubl  v9.8h, v13.8b, v14.8b
+v9:
+usubl2 v9.8h, v13.16b, v14.16b
+v9:
+usubl  v9.4s, v13.4h, v14.4h
+v9:
+usubl2 v9.4s, v13.8h, v14.8h
+v9:
+usubl  v9.2d, v13.2s, v14.2s
+v9:
+usubl2 v9.2d, v13.4s, v14.4s
+v9:
+uabdl  v9.8h, v13.8b, v14.8b
+v9:
+uabdl2 v9.8h, v13.16b, v14.16b
+v9:
+uabdl  v9.4s, v13.4h, v14.4h
+v9:
+uabdl2 v9.4s, v13.8h, v14.8h
+v9:
+uabdl  v9.2d, v13.2s, v14.2s
+v9:
+uabdl2 v9.2d, v13.4s, v14.4s
+v9:
+umull  v9.8h, v13.8b, v14.8b
+v9:
+umull2 v9.8h, v13.16b, v14.16b
+v9:
+umull  v9.4s, v13.4h, v14.4h
+v9:
+umull2 v9.4s, v13.8h, v14.8h
+v9:
+umull  v9.2d, v13.2s, v14.2s
+v9:
+umull2 v9.2d, v13.4s, v14.4s
+v9:
+smull  v9.8h, v13.8b, v14.8b
+v9:
+smull2 v9.8h, v13.16b, v14.16b
+v9:
+smull  v9.4s, v13.4h, v14.4h
+v9:
+smull2 v9.4s, v13.8h, v14.8h
+v9:
+smull  v9.2d, v13.2s, v14.2s
+v9:
+smull2 v9.2d, v13.4s, v14.4s
+v9:
