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[209.132.180.131]) by mx.google.com with ESMTPS id 75si31991306iol.1.2015.10.08.07.07.01 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Oct 2015 07:07:02 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-409621-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 100332 invoked by alias); 8 Oct 2015 14:06:48 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 100322 invoked by uid 89); 8 Oct 2015 14:06:47 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL, BAYES_00, SPF_PASS, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 08 Oct 2015 14:06:45 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7B8933C for ; Thu, 8 Oct 2015 07:06:43 -0700 (PDT) Received: from e105545-lin (e105545-lin.cambridge.arm.com [10.2.206.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9C17F3F236 for ; Thu, 8 Oct 2015 07:06:43 -0700 (PDT) Date: Thu, 8 Oct 2015 15:06:38 +0100 From: Ramana Radhakrishnan To: gcc-patches@gcc.gnu.org Subject: [Patch PR target/67366 1/2] [ARM] - Add movmisalignhi / si patterns Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-Original-Sender: ramana.radhakrishnan@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::234 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 This adds movmisalignhi and movmisalignsi expanders when unaligned access is allowed by the architecture. This allows the mid-end to expand to misaligned loads and stored. Compared code generated for the Linux kernel and it changes code generation for a handful of files all for the better basically by reducing the stack usage. Tested by : 1. armhf bootstrap and regression test - no regressions. 2.. arm-none-eabi cross build and regression test for {-marm/-march=armv7-a/-mfpu=vfpv3-d16/-mfloat-abi=softfp} {-mthumb/-march=armv8-a/-mfpu=crypto-neon-fp-armv8/-mfloat-abi=hard} {-marm/-mcpu=arm7tdmi/-mfloat-abi=soft} {-mthumb/-mcpu=arm7tdmi/-mfloat-abi=soft} Will apply to trunk once 2/2 is approved. regards Ramana 2015-09-15 Ramana Radhakrishnan PR target/67366 * config/arm/arm.md (movmisalign): New. * config/arm/iterators.md (HSI): New. --- gcc/config/arm/arm.md | 35 +++++++++++++++++++++++++++++++++++ gcc/config/arm/iterators.md | 3 +++ 2 files changed, 38 insertions(+) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index b4c555b..9a3f7bd 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -11506,6 +11506,41 @@ }" ) +;; movmisalign patterns for HImode and SImode. +(define_expand "movmisalign" + [(match_operand:HSI 0 "general_operand") + (match_operand:HSI 1 "general_operand")] + "unaligned_access" +{ + /* This pattern is not permitted to fail during expansion: if both arguments + are non-registers (e.g. memory := constant), force operand 1 into a + register. */ + rtx (* gen_unaligned_load)(rtx, rtx); + rtx tmp_dest = operands[0]; + if (!s_register_operand (operands[0], mode) + && !s_register_operand (operands[1], mode)) + operands[1] = force_reg (mode, operands[1]); + + if (mode == HImode) + { + gen_unaligned_load = gen_unaligned_loadhiu; + tmp_dest = gen_reg_rtx (SImode); + } + else + gen_unaligned_load = gen_unaligned_loadsi; + + if (MEM_P (operands[1])) + { + emit_insn (gen_unaligned_load (tmp_dest, operands[1])); + if (mode == HImode) + emit_move_insn (operands[0], gen_lowpart (HImode, tmp_dest)); + } + else + emit_insn (gen_unaligned_store (operands[0], operands[1])); + + DONE; +}) + ;; Vector bits common to IWMMXT and Neon (include "vec-common.md") ;; Load the Intel Wireless Multimedia Extension patterns diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 47cc1ee..6a54125 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -33,6 +33,9 @@ ;; A list of integer modes that are up to one word long (define_mode_iterator QHSI [QI HI SI]) +;; A list of integer modes that are half and one word long +(define_mode_iterator HSI [HI SI]) + ;; A list of integer modes that are less than a word (define_mode_iterator NARROW [QI HI])