From patchwork Tue Dec 13 17:35:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 87915 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp2327437qgi; Tue, 13 Dec 2016 09:35:51 -0800 (PST) X-Received: by 10.84.174.67 with SMTP id q61mr193446417plb.93.1481650551192; Tue, 13 Dec 2016 09:35:51 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id 19si48753555pfr.164.2016.12.13.09.35.50 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 13 Dec 2016 09:35:51 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-444318-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-444318-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-444318-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=p7rovGpQh8pL2ZHfsIHutYcWOftTHfXdUArjb1hyj6/LjxUXXT QS0czuMjoI0+sl24wGq1FpYpTWoNHUEi3nXZfrj6emRNWz6Yc5O3j0t6+jw2656Q 54hkyTxwq3/yhIRmGU37TlQH8gJxvRkp3AvHmioyd1YiSmBqkkroQQ+u8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; s= default; bh=fV4NWk3VwPAZ4SdE2KohAfhBtVY=; b=ZuEagUSPkWL4Mgts3on2 9wJXMbk5SX+jK6xB8hsQoic9JXxKUd02BMMmRhpGJ5YQmewSXG9sA4uIwoiyBB3F wpEfIP7dtpmQ1SbiSD+EJGwztx/GW78YQZUxp+dDuHSH8QpIy+esR/HGS8YoEsnC VWqY2jpyqsftqgnkzIvM1+o= Received: (qmail 36613 invoked by alias); 13 Dec 2016 17:35:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 36561 invoked by uid 89); 13 Dec 2016 17:35:38 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-4.0 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=sk:embedde X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 13 Dec 2016 17:35:28 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CA484F; Tue, 13 Dec 2016 09:35:26 -0800 (PST) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7A7FD3F45C for ; Tue, 13 Dec 2016 09:35:26 -0800 (PST) To: "gcc-patches@gcc.gnu.org" From: Thomas Preudhomme Subject: [arm-embedded] Add ARMv8-M Security Extensions support to Cortex-M23 and Cortex-M33 Message-ID: Date: Tue, 13 Dec 2016 17:35:25 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 X-IsSubscribed: yes Hi, We have decided to apply the following patch to the embedded-6-branch to enable ARMv8-M Security Extensions to ARM Cortex-M23 and ARM Cortex-M33. ChangeLog entry is as follows: *** gcc/ChangeLog *** 2016-12-13 Thomas Preud'homme * config/arm/arm-cores.def (cortex-m23): Add FL2_CMSE flag. (cortex-m33): Likewise. I've checked that gcc.target/arm/cmse/cmse-1.c compiles with -mcpu=cortex-m23 -mcmse and -mcpu=cortex-m33 and that it does not when trying with -mcpu=cortex-m0 -mcmse or -mcpu=cortex-m7 -mcmse. Best regards, Thomas diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index e5b492897a7b39ade9286e6b8b15934277a6848e..add6b21ee5238aab5759d17f3de1aa5dff928d7f 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -166,9 +166,9 @@ ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, 7A, ARM_FSET_MAKE_ ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12) /* V8 Architecture Processors */ -ARM_CORE("cortex-m23", cortexm23, cortexm23, 8M_BASE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8M_BASE), v6m) +ARM_CORE("cortex-m23", cortexm23, cortexm23, 8M_BASE, ARM_FSET_MAKE (FL_LDSCHED | FL_FOR_ARCH8M_BASE, FL2_CMSE), v6m) ARM_CORE("cortex-a32", cortexa32, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a35) -ARM_CORE("cortex-m33", cortexm33, cortexm33, 8M_MAIN, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN), v7m) +ARM_CORE("cortex-m33", cortexm33, cortexm33, 8M_MAIN, ARM_FSET_MAKE (FL_LDSCHED | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN, FL2_CMSE), v7m) ARM_CORE("cortex-a35", cortexa35, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a35) ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a53) ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)