From patchwork Mon Jul 3 13:23:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 106899 Delivered-To: patch@linaro.org Received: by 10.182.135.102 with SMTP id pr6csp9392693obb; Mon, 3 Jul 2017 06:23:59 -0700 (PDT) X-Received: by 10.98.18.143 with SMTP id 15mr9917219pfs.163.1499088239443; Mon, 03 Jul 2017 06:23:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1499088239; cv=none; d=google.com; s=arc-20160816; b=aL5VmDg8mqffM5Vm33OvwRjBpkpgzWdXHrgO9DKpKm8k/MbyPp2NEXvTtNxM+cDi8S DCJNiBpOc6WDW8swtXDKWyMJey4EaqHCMVMrjaZF/6UcxfA14E7PwTHnE3l1Rl8fLK5E rVb0T/kiDwDm3zf/WquuNp8dIWUGhX0fv5Cie7eOM3PSZhgdmOTgCy+0yT/NEmegzEjN YMr+HAIklLhru23f5qyBwGw8NQNVKf0SOJ7ErigTrhdH5+FKy5mOxpJja9pG4pinY/ey bkfgJ096p/trBBev05kf3p9QintbZ4SJ6YueorWKQ68weiCeC6XQEt+wnEAKoT9gm5nH QmjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:user-agent:date:message-id:subject:from:to :delivered-to:sender:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature:arc-authentication-results; bh=/Wq0+FwmRiN53R71kZjWvQyqNbrO5n1CPmL2/KvCwxc=; b=IABpCT0otLF9q7c9YMpUzEr3ypkqlTzNinhyXyTMhAKrwqTkyjMRz003mWDaQAJH19 dJO1K7AZLbDvfqPgbvd76N32IZI+9egc8Lt3O3aOSpaspkZo8033AyhfRaou2h5yJ5CV jHbpMjiR3GuYXtrfvpMjMbS7UWMsvFYT4giE3YbR5B6ZoUwvT8YwdZ8kuHXIMhZJLN6v 909x6HKPOzJiWYUFqslPWsJkb/SevMOX1lsu8x9ZxBm8Dby6U4ZMO0fSWCDEpkNFQrdh 26ldJHSc+/ZoeTmfjkDfGBmzi3+71H+BXjjm15hjk3ph2YLOnsIrQJ9YTsSAWUvMrEMn SqPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.b=OzT9GG6F; spf=pass (google.com: domain of gcc-patches-return-457446-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-457446-patch=linaro.org@gcc.gnu.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id w185si12142921pgb.102.2017.07.03.06.23.58 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Jul 2017 06:23:59 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-457446-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.b=OzT9GG6F; spf=pass (google.com: domain of gcc-patches-return-457446-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-457446-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=K8K135gMTl80CKtnQLubvChlOY9VApaD62+b1Bfe8TmuHFZ04l 07WpOdFe29HJyS6QJuLk0NaDIPSJ0lex/V+oS9cTHOR4oLk3pFl8l3mltd94kLWt DfVUmFAmqYh9gb4jBLOA2loDF8FLpbpmHQ4S6LSiVhHGR349uU9Deh1Ms= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; s= default; bh=NO7K/DJpgT8unsLw97/HynCrHpw=; b=OzT9GG6FD+4MrWw4fqc1 6uX6h/rAQdgYkK2830tyEagGHAzV6SyFfqLn9QveZdGCQv7N+RKqZSlF04GI7xbN dT3fvs4N4v4juFJWeNLrZHePNWWuPfegsmwWyknsiG8SaMYwO3sBMSHRCbJcE3qY s0edRSXpf32w5J/ntA2LbVg= Received: (qmail 7438 invoked by alias); 3 Jul 2017 13:23:37 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 7007 invoked by uid 89); 3 Jul 2017 13:23:36 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy=abis, ABIs, deliberate, whilst X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 03 Jul 2017 13:23:33 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 75A2D344; Mon, 3 Jul 2017 06:23:31 -0700 (PDT) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 050B83F578; Mon, 3 Jul 2017 06:23:30 -0700 (PDT) To: gcc-patches From: "Richard Earnshaw (lists)" Subject: [patch][arm] Clean up generation of BE8 format images. Message-ID: Date: Mon, 3 Jul 2017 14:23:23 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 The existing code in arm/bpabi.h was quite fragile and relied on matching specific CPU and/or architecture names. The introduction of the option format for -mcpu and -march broke that in a way that would be non-trivial to fix by updating the list. The hook in that file was always a pain as it required every new CPU being added to be add an update here as well (easy to miss). I've fixed that problem once and for all by adding a new callback into the driver to select the correct BE8 behaviour. This uses features in the ISA capabilities list to select whether or not to use BE8 format during linking. I also noticed that if the user happened to pass both -mbig-endian and -mlittle-endian on the command line then the linker spec rules would get somewhat confused and potentially do the wrong thing. I've fixed that by marking these options as opposites in the option descriptions. The driver will now automatically suppress overridden options leading to the correct desired behavior. Whilst fixing this I noticed a couple of anomolus cases in the existing BE8 support: we were not generating BE8 format for ARMv6 or ARMv7-R targets. While the ARMv6 status was probably deliberate at the time, this is probably not a good idea in the long term as the alternative, BE32, has been deprecated by ARM. After discussion with a couple of colleagues I've decided to change this, but to then add an option to restore the existing behaviour at the user's option. So this patch introduces two new options (opposites) -mbe8 and -mbe32. This is a quiet behavior change, so I'll add a comment to the release notes shortly. * common/config/arm/arm-common.c (arm_be8_option): New function. * config/arm/arm-isa.h (isa_feature): Add new feature bit isa_bit_be8. (ISA_ARMv6): Add isa_bit_be8. * config/arm/arm.h (arm_be8_option): Add prototype. (BE8_SPEC_FUNCTION): New define. (EXTRA_SPEC_FUNCTIONS): Add BE8_SPEC_FUNCTION. * config/arm/arm.opt (mbig-endian): Mark as Negative of mlittle-endian. (mlittle-endian): Similarly. (mbe8, mbe32): New options. * config/arm/bpabi.h (BE8_LINK_SPEC): Call arm_be8_option. * doc/invoke.texi (ARM Options): Document -mbe8 and -mbe32. diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c index d06c39b..b6244d6 100644 --- a/gcc/common/config/arm/arm-common.c +++ b/gcc/common/config/arm/arm-common.c @@ -761,6 +761,63 @@ arm_canon_arch_option (int argc, const char **argv) return canonical_arch; } +/* If building big-endian on a BE8 target generate a --be8 option for + the linker. Takes four types of option: "little" - little-endian; + "big" - big-endian; "be8" - force be8 iff big-endian; and "arch" + "" (two arguments) - the target architecture. The + parameter names are generated by the driver from the command-line + options. */ +const char * +arm_be8_option (int argc, const char **argv) +{ + int endian = TARGET_ENDIAN_DEFAULT; + const char *arch = NULL; + int arg; + bool force = false; + + for (arg = 0; arg < argc; arg++) + { + if (strcmp (argv[arg], "little") == 0) + endian = 0; + else if (strcmp (argv[arg], "big") == 0) + endian = 1; + else if (strcmp (argv[arg], "be8") == 0) + force = true; + else if (strcmp (argv[arg], "arch") == 0) + { + arg++; + gcc_assert (arg < argc); + arch = argv[arg]; + } + else + gcc_unreachable (); + } + + /* Little endian - no be8 option. */ + if (!endian) + return ""; + + if (force) + return "--be8"; + + /* Arch might not be set iff arm_canon_arch (above) detected an + error. Do nothing in that case. */ + if (!arch) + return ""; + + const arch_option *selected_arch + = arm_parse_arch_option_name (all_architectures, "-march", arch); + + /* Similarly if the given arch option was itself invalid. */ + if (!selected_arch) + return ""; + + if (check_isa_bits_for (selected_arch->common.isa_bits, isa_bit_be8)) + return "--be8"; + + return ""; +} + #undef ARM_CPU_NAME_LENGTH diff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h index 4b5a0f6..c0c2cce 100644 --- a/gcc/config/arm/arm-isa.h +++ b/gcc/config/arm/arm-isa.h @@ -40,7 +40,8 @@ enum isa_feature isa_bit_ARMv6, /* Architecture rel 6. */ isa_bit_ARMv6k, /* Architecture rel 6k. */ isa_bit_thumb2, /* Thumb-2. */ - isa_bit_notm, /* Instructions that are not present in 'M' profile. */ + isa_bit_notm, /* Instructions not present in 'M' profile. */ + isa_bit_be8, /* Architecture uses be8 mode in big-endian. */ isa_bit_tdiv, /* Thumb division instructions. */ isa_bit_ARMv7em, /* Architecture rel 7e-m. */ isa_bit_ARMv7, /* Architecture rel 7. */ @@ -101,7 +102,7 @@ enum isa_feature #define ISA_ARMv5e ISA_ARMv5, isa_bit_ARMv5e #define ISA_ARMv5te ISA_ARMv5e, isa_bit_thumb #define ISA_ARMv5tej ISA_ARMv5te -#define ISA_ARMv6 ISA_ARMv5te, isa_bit_ARMv6 +#define ISA_ARMv6 ISA_ARMv5te, isa_bit_ARMv6, isa_bit_be8 #define ISA_ARMv6j ISA_ARMv6 #define ISA_ARMv6k ISA_ARMv6, isa_bit_ARMv6k #define ISA_ARMv6z ISA_ARMv6 diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 6bc36bba..c803d44 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2257,11 +2257,16 @@ const char *arm_canon_arch_option (int argc, const char **argv); #define CANON_ARCH_SPEC_FUNCTION \ { "canon_arch", arm_canon_arch_option }, +const char *arm_be8_option (int argc, const char **argv); +#define BE8_SPEC_FUNCTION \ + { "be8_linkopt", arm_be8_option }, + # define EXTRA_SPEC_FUNCTIONS \ MCPU_MTUNE_NATIVE_FUNCTIONS \ ASM_CPU_SPEC_FUNCTIONS \ CANON_ARCH_SPEC_FUNCTION \ - TARGET_MODE_SPEC_FUNCTIONS + TARGET_MODE_SPEC_FUNCTIONS \ + BE8_SPEC_FUNCTION /* Automatically add -mthumb for Thumb-only targets if mode isn't specified via the configuration option --with-mode or via the command line. The diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt index dad5257..b6c707b 100644 --- a/gcc/config/arm/arm.opt +++ b/gcc/config/arm/arm.opt @@ -95,7 +95,7 @@ Target Report RejectNegative Negative(mthumb) InverseMask(THUMB) Generate code in 32 bit ARM state. mbig-endian -Target Report RejectNegative Mask(BIG_END) +Target Report RejectNegative Negative(mlittle-endian) Mask(BIG_END) Assume target CPU is configured as big endian. mcallee-super-interworking @@ -160,7 +160,7 @@ mhard-float Target RejectNegative Alias(mfloat-abi=, hard) Undocumented mlittle-endian -Target Report RejectNegative InverseMask(BIG_END) +Target Report RejectNegative Negative(mbig-endian) InverseMask(BIG_END) Assume target CPU is configured as little endian. mlong-calls @@ -286,3 +286,11 @@ Assume unified syntax for inline assembly code. mpure-code Target Report Var(target_pure_code) Init(0) Do not allow constant data to be placed in code sections. + +mbe8 +Target Report RejectNegative Negative(mbe32) Mask(BE8) +When linking for big-endian targets, generate a BE8 format image. + +mbe32 +Target Report RejectNegative Negative(mbe8) InverseMask(BE8) +When linking for big-endian targets, generate a legacy BE32 format image. diff --git a/gcc/config/arm/bpabi.h b/gcc/config/arm/bpabi.h index d38863a..2f41c4f 100644 --- a/gcc/config/arm/bpabi.h +++ b/gcc/config/arm/bpabi.h @@ -26,7 +26,7 @@ /* Use the AAPCS ABI by default. */ #define ARM_DEFAULT_ABI ARM_ABI_AAPCS -/* Assume that AAPCS ABIs should adhere to the full BPABI. */ +/* Assume that AAPCS ABIs should adhere to the full BPABI. */ #define TARGET_BPABI (TARGET_AAPCS_BASED) /* BPABI targets use EABI frame unwinding tables. */ @@ -55,84 +55,11 @@ #define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*"\ "|march=armv4|mcpu=fa526|mcpu=fa626:--fix-v4bx}" -#if TARGET_BIG_ENDIAN_DEFAULT -#define BE8_LINK_SPEC \ - " %{!mlittle-endian:%{march=armv7-a|mcpu=cortex-a5 \ - |mcpu=cortex-a7 \ - |mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15 \ - |mcpu=cortex-a12|mcpu=cortex-a17 \ - |mcpu=cortex-a15.cortex-a7 \ - |mcpu=cortex-a17.cortex-a7 \ - |mcpu=marvell-pj4 \ - |mcpu=cortex-a32 \ - |mcpu=cortex-a35 \ - |mcpu=cortex-a53 \ - |mcpu=cortex-a57 \ - |mcpu=cortex-a57.cortex-a53 \ - |mcpu=cortex-a72 \ - |mcpu=cortex-a72.cortex-a53 \ - |mcpu=cortex-a73 \ - |mcpu=cortex-a73.cortex-a35 \ - |mcpu=cortex-a73.cortex-a53 \ - |mcpu=exynos-m1 \ - |mcpu=xgene1 \ - |mcpu=cortex-m1.small-multiply \ - |mcpu=cortex-m0.small-multiply \ - |mcpu=cortex-m0plus.small-multiply \ - |mcpu=generic-armv7-a \ - |march=armv7ve \ - |march=armv7-m|mcpu=cortex-m3 \ - |march=armv7e-m|mcpu=cortex-m4|mcpu=cortex-m7 \ - |march=armv6-m|mcpu=cortex-m0 \ - |march=armv8-a \ - |march=armv8-a+crc \ - |march=armv8.1-a \ - |march=armv8.1-a+crc \ - |march=armv8.2-a \ - |march=armv8.2-a+fp16 \ - |march=armv8-m.base|mcpu=cortex-m23 \ - |march=armv8-m.main \ - |march=armv8-m.main+dsp|mcpu=cortex-m33 \ - :%{!r:--be8}}}" -#else -#define BE8_LINK_SPEC \ - " %{mbig-endian:%{march=armv7-a|mcpu=cortex-a5 \ - |mcpu=cortex-a7 \ - |mcpu=cortex-a8|mcpu=cortex-a9|mcpu=cortex-a15 \ - |mcpu=cortex-a12|mcpu=cortex-a17 \ - |mcpu=cortex-a15.cortex-a7 \ - |mcpu=cortex-a17.cortex-a7 \ - |mcpu=cortex-a35 \ - |mcpu=cortex-a53 \ - |mcpu=cortex-a57 \ - |mcpu=cortex-a57.cortex-a53 \ - |mcpu=cortex-a72 \ - |mcpu=cortex-a72.cortex-a53 \ - |mcpu=cortex-a73 \ - |mcpu=cortex-a73.cortex-a35 \ - |mcpu=cortex-a73.cortex-a53 \ - |mcpu=exynos-m1 \ - |mcpu=xgene1 \ - |mcpu=cortex-m1.small-multiply \ - |mcpu=cortex-m0.small-multiply \ - |mcpu=cortex-m0plus.small-multiply \ - |mcpu=marvell-pj4 \ - |mcpu=generic-armv7-a \ - |march=armv7ve \ - |march=armv7-m|mcpu=cortex-m3 \ - |march=armv7e-m|mcpu=cortex-m4|mcpu=cortex-m7 \ - |march=armv6-m|mcpu=cortex-m0 \ - |march=armv8-a \ - |march=armv8-a+crc \ - |march=armv8.1-a \ - |march=armv8.1-a+crc \ - |march=armv8.2-a \ - |march=armv8.2-a+fp16 \ - |march=armv8-m.base|mcpu=cortex-m23 \ - |march=armv8-m.main \ - |march=armv8-m.main+dsp|mcpu=cortex-m33 \ - :%{!r:--be8}}}" -#endif +#define BE8_LINK_SPEC \ + "%{!r:%{!mbe32:%:be8_linkopt(%{mlittle-endian:little}" \ + " %{mbig-endian:big}" \ + " %{mbe8:be8}" \ + " %{march=*:arch %*})}}" /* Tell the assembler to build BPABI binaries. */ #undef SUBTARGET_EXTRA_ASM_SPEC diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index d1e097b..bef92a82 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -15188,6 +15188,15 @@ the default for all standard configurations. Generate code for a processor running in big-endian mode; the default is to compile code for a little-endian processor. +@item -mbe8 +@itemx -mbe32 +@opindex mbe8 +When linking a big-endian image select between BE8 and BE32 formats. +The option has no effect for little-endian images and is ignored. The +default is dependent on the selected target architecture. For ARMv6 +and later architectures the default is BE8, for older architectures +the default is BE32. BE32 format has been deprecated by ARM. + @item -march=@var{name@r{[}+extension@dots{}@r{]}} @opindex march This specifies the name of the target ARM architecture. GCC uses this